메뉴 건너뛰기




Volumn 1166, Issue , 1996, Pages 49-63

Modular verification of multipliers

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LOGIC CIRCUITS; RECONFIGURABLE HARDWARE;

EID: 84957679160     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0031799     Document Type: Conference Paper
Times cited : (7)

References (21)
  • 1
    • 0026280474 scopus 로고
    • Boolean satisfiability and equivalence checking using general binary decision diagrams
    • Cambridge, MA, October
    • P. Ashar, A. Ghosh, and S. Devadas. Boolean satisfiability and equivalence checking using general binary decision diagrams. In Proceedings of the International Conference on Computer Design, pages 259-264, Cambridge, MA, October 1991.
    • (1991) Proceedings of the International Conference on Computer Design , pp. 259-264
    • Ashar, P.1    Ghosh, A.2    Devadas, S.3
  • 5
    • 0003961449 scopus 로고
    • Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of California
    • R. K. Brayton et al. VIS: A system for verification and synthesis. Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of California, December 1995.
    • (1995) VIS: A System for Verification and Synthesis
    • Brayton, R.K.1
  • 6
    • 0029224152 scopus 로고
    • Verification of arithmetic circuits with binary moment diagrams
    • San Francisco, CA
    • R. Bryant and Y.-A. Chen. Verification of arithmetic circuits with binary moment diagrams. In Proceedings of the Design Automation Conference, pages 535-541, San Francisco, CA, June 1995.
    • (1995) Proceedings of the Design Automation Conference , pp. 535-541
    • Bryant, R.1    Chen, Y.-A.2
  • 7
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35(8):677-691, August 1986.
    • (1986) IEEE Transactions on Computers , vol.35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 8
    • 0026107125 scopus 로고
    • On the complexity of VLSI implementations and graph representations of boolean functions with application to integer multiplication
    • R. E. Bryant. On the complexity of VLSI implementations and graph representations of boolean functions with application to integer multiplication. IEEE Transactions on Computers, 40(2):205-213, February 1991.
    • (1991) IEEE Transactions on Computers , vol.40 , Issue.2 , pp. 205-213
    • Bryant, R.E.1
  • 17
    • 0029224999 scopus 로고
    • Residue BDD and its application to the verification of arithmetic circuits
    • San Francisco, CA
    • S. Kimura. Residue BDD and its application to the verification of arithmetic circuits. In Proceedings of the Design Automation Conference, pages 542-545, San Francisco, CA, June 1995.
    • (1995) Proceedings of the Design Automation Conference , pp. 542-545
    • Kimura, S.1
  • 18
    • 0026992526 scopus 로고
    • Edge-valued binary decision diagrams for multilevel hierarchical verification
    • Anaheim, CA
    • Y.-T. Lai and S. Sastry. Edge-valued binary decision diagrams for multilevel hierarchical verification. In Proceedings of the Design Automation Conference, pages 608-613, Anaheim, CA, June 1992.
    • (1992) Proceedings of the Design Automation Conference , pp. 608-613
    • Lai, Y.-T.1    Sastry, S.2
  • 19
    • 0027211369 scopus 로고
    • Zero-suppressed BDDs for set manipulation in combinatorial problems
    • Dallas, TX
    • S.-I. Minato. Zero-suppressed BDDs for set manipulation in combinatorial problems. In Proceedings of the Design Automation Conference, pages 272-277, Dallas, TX, June 1993.
    • (1993) Proceedings of the Design Automation Conference , pp. 272-277
    • Minato, S.-I.1
  • 20
    • 0028380923 scopus 로고
    • Extended BDDs: Trading off canonicity forstructure in verification algorithms
    • B. Plessier, G. Hachtel, and F. Somenzi. Extended BDDs: Trading off canonicity for structure in verification algorithms. Journal of Formal Methods in System Design, 4(2):167-185, February 1994.
    • (1994) Journal of Formal Methods in System Design , vol.4 , Issue.2 , pp. 167-185
    • Plessier, B.1    Hachtel, G.2    Somenzi, F.3
  • 21
    • 0029214437 scopus 로고
    • Novel verification framework combining structural and OBDD methods in a synthesis environment
    • San Francisco, CA
    • S. M. Reddy, W. Kunz, and D. K. Pradhan. Novel verification framework combining structural and OBDD methods in a synthesis environment. In Proceedings of the Design Automation Conference, pages 414-419, San Francisco, CA, June 1995.
    • (1995) Proceedings of the Design Automation Conference , pp. 414-419
    • Reddy, S.M.1    Kunz, W.2    Pradhan, D.K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.