MorphoSys: A reconfigurable processor targeted to high performance image application

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1586, Issue , 1999, Pages 661-669

  Lu, Guangming ^a   Lee, Ming Hau ^a   Singh, Hartej ^a   Bagherzadeh, Nader ^a   Kurdahi, Fadi J ^a   Filho, Eliseu M ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b FEDERAL UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; REDUCED INSTRUCTION SET COMPUTING;

COARSE-GRAINED RECONFIGURABLE; DESIGN IDEAS; IMAGE APPLICATIONS; PERFORMANCE ENHANCEMENTS; RECONFIGURABLE COMPUTING; RECONFIGURABLE PROCESSORS; RISC PROCESSORS; SIMD ARCHITECTURE;

PARALLEL PROCESSING SYSTEMS;

EID: 84957660371     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0097951     Document Type: Conference Paper

References (17)

1. E. Tau, D. Chen, I. Eslick, J. Brown, A. DeHon, “A First Generation DPGA Implementation”. FPD’95 Third Canadian Workshop of Field-Programmable Devices, May 1995.
2. J. R. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Reconfigurable Coprocessor,” Proc. of the 1EEE Symposium on FPGAs for Custom Computing Machines, 1997
3. E. Mirsky and A. DeHon, “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, 1996, pp. 157-66.
4. C. Ebeling, D. Cronquist, and P. Franklin, “Configurable Computing: The Catalyst for High-Performance Architectures,” Proeedings of lEEE Internatinoat Conference on Application specific Systems, Architectures and Processors, July 1997, pp. 364-72.
5. J. Babb, M. Frank, V. Lee, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, A. Agrawal, “The RAW Benchmark Suite: computation structures for general-purpose computing,” Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 97, 1997, pp. 134-43.
6. A. Abnous, C. Christensen, J. Gray, J. Lenell, A. Naylor and N. Bagherzaheh, “Design and implementation of the TinyRISC microprocessor” Microprocessors and Microsystems. VoL 16, No.4, pp.187-94, 1992.
7. Stanford PVRG-MPEG by anonymous ftp from havefun.stanford.edu:/pub/mpeg/MPEGv 1.2.tar.Z.
8. SUIF Compiler system, The Stanford SUIF Compiler Group, http://suifstanford.edu
9. MPEG2 Standard. http://www.mpeg.org.
10. C. Hsieh, T. Lin, “VLSI Architecture For Block Matching Motion Estimation Algorithm” IEEE Transaction on CSVT, Vol. 2, June, 1992.
11. S.H. Name, J.S. Baek, T.Y. Lee, M.K. Lee, “A VLSI Design For Full Search Block Matching Motion Estimation” Proceedings of IEEE ASIC Conference, Rochester, NY, Set 1994.
12. K-M Yang, M-T Sun, and L. Wu, “A Family of VLSI Designs for Motion Compensation Block Matching Algorithm” IEEE Transaction on Circuits and Systems. Vol 36. No.10, Oct 89.
13. Intel Application Notes for Pentium MMX. http://dm,eloper.intel.com/drg/mmx/appnotes.
14. T. Miyamori and K. Olnkotun, “A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, “‘ Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, April 1998
15. J. Villasenor, B. Schoner, K. Chia, C. Zapata, H. J. Kim, C. Jones, S. Lansing, and B. Mangione-Smith “Configurable Computing Solutions for Automatic Target Recognition” Proceedings of lEEE Workshop on FPGAs For Custom Computing Machines, April 1996.
16. M. Rencher and B.L. Hutchings, “Automatic Target Recognition on SPLASH 2” Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, April 1997.
17. H. Singh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, T. Lang, R. Heaton, E. Filho, “MorphoSys: An Integrated Re-configurable Architecture” Proceeding of the NATO Symposium on Concepts and lntegration, April, 1998.