A structural approach for the analysis of Petri Nets by reduced unfoldings

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1091, Issue , 1996, Pages 346-365

  Kondratyev, Alex ^a   Kishinevsky, Michael ^a   Taubin, Alexander ^a   Ten, Sergei ^a  

^a UNIVERSITY OF AIZU   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; PETRI NETS;

ASYNCHRONOUS DESIGN; CIRCUIT BEHAVIORS; CORRESPONDING STATE; ORDERS OF MAGNITUDE; SIGNAL TRANSITION; SIGNAL TRANSITION GRAPHS; STATE EXPLOSION PROBLEMS; STRUCTURAL APPROACH;

ELECTRIC NETWORK ANALYSIS;

EID: 84957620669     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61363-3_19     Document Type: Conference Paper

References (22)

1. T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, June 1987.
2. J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Synthesizing Petri nets from state-based models. In Proceedings of the International Conference on Computer-Aided Design, November 1995. to appear.
3. J. Esparza. Model checking using net unfoldings. In M.-C. Gaudel and J.-P. Jouannaud, editors, TAPSOFT'93: Theory and Practice of Software Development, 4th Int. Joint Conference CAAP/FASE, volume 668 of Lecture Notes in Computer Science, pages 613-628. Springer-Verlag, 1993.
4. T. Esparza, S. Romer, and W. Vogler. An improvement of mcmillan's unfolding algorithm. Technical Report TUM: 19599, Technische Universität München, August 1995.
5. M. A. Kishinevsky, A. Y. Kondratyev, A. R. Taubin, and V. I. Varshavsky. Concurrent Hardware. The Theory and Practice of Self-Timed Design. John Wiley and Sons Ltd., 1994.
6. A. Kondratyev, J. Cortadella, M. Kishinevsky, E. Pastor, O. Roig, and A. Yakovlev. Checking Signal Transition Graph implementability by symbolic BDD traversal. In Proceedings of the European Design and Test Conference (ED&TC), pages 325-332, Paris, France, March 1995.
7. A. Kondratyev, M. Kishinevsky, A. Taubin, and S. Ten. Analysis of Petri nets by ordering relations in reduced unfoldings. Technical Report TR:95-2-002, The University of Aizu, June 1995.
8. A. Kondratyev and A. Taubin. Verification of speed-independent circuits by STG unfoldings. In Proceedings of the Symposium on Advanced Reserch in Asynchronous Cirsuits and Systems, pages 64-75, Utah, USA, November 1994.
9. L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for synthesis and testing of asynchronous circuits. Kluwer Academic Publishers, 1993.
10. K. McMillan. A technique of state space search based on unfolding. Formal Methods in System Design, 6(l):45-65, 1995.
11. T. H.-Y. Meng. Synchronization Design for Digital Systems. Kluwer Academic Publishers, 1991. Contributions by David Mes David Dill.
12. D. E. Muller. Asynchronous logics and application to information processing. In Proc. Symp. on Application of Switching Theory in Space Technology, pages 289-297. Stanford University Press, 1963.
13. D. E. Muller and W. C. Bartky. A theory of asynchronous circuits. In Annals of Computing Laboratory of Harvard University, pages 204-243, 1959.
14. T. Murata. Petri nets: Properties, analysis and applications. Proceedings of IEEE, 77(4):541-580, April 1989.
15. M. Nielsen, G. Plotkin, and Winskel G. Events structures and domains. Theoretical Computer Science, 13(1):85-108, 1980.
16. E. Pastor, O. Roig, J. Cortadella, and R. Badia. Petri net analysis using boolean manipulation. In 15th International Conference on Application and Theory of Petri Nets, pages 416-435, Zaragoza, Spain, June 1994.
17. S. Patil and J. Dennis. The description and realization of digital systems. In Proceedings of the IEEE COMPCON, pages 223-226, N.Y., 1972.
18. L. Pomello, G. Rozenberg, and C. Simone. A survey of equivalence notions for net based systems. Lecture Notes in Computer Science, 609:410-472, 1993.
19. A. Semenov and A. Yakovlev. Event-based framework for verifying high-level models of asynchronous circuits. Technical Report TR No.487, Computing Science, University of Newcastle upon Tyne, June 1994.
20. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, U.C. Berkeley, May 1992.
21. A. Valmari. State of the art report: Stubborn sets. Petri Nets Newsletter, (46):6-14,1994.
22. A. Yakovlev, M. Kishinevsky, A. Kondratyev, and L. Lavagno. OR causality: modelling and hardware implementation. In Proceedings of the 15th International Conference on Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, pages 568-587, Zaragosa, Spain, June 1994. Springer-Verlag.