Verification of asynchronous circuits by BDD-based model checking of petri nets

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 935, Issue , 1995, Pages 374-391

  Roig, Oriol ^a   Cortadella, Jordi ^a   Pastor, Enric ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; PETRI NETS; SPECIFICATIONS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; CIRCUIT PROPERTIES; GATE LEVELS; NETWORK BEHAVIORS; SPEED INDEPENDENT; SYMBOLIC REACHABILITY ANALYSIS; VERIFICATION METHOD;

MODEL CHECKING;

EID: 84956869194     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-60029-9_50     Document Type: Conference Paper

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