Exploiting the prefetching effect provided by executing mispredicted load instructions

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2400, Issue , 2002, Pages 468-480

  Sendag, Resit ^a   Lilja, David J ^a   Kunkel, Steven R ^b  

^a University of Minnesota   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL PROCESSING SYSTEMS;

CACHE POLLUTION; CONDITIONAL BRANCH; INSTRUCTION FETCH; INSTRUCTION LEVEL PARALLELISM; MEMORY PERFORMANCE; MISPREDICTED LOADS; PATH EXECUTION; SUPERSCALAR ARCHITECTURE;

CACHE MEMORY;

EID: 84956866618     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45706-2_64     Document Type: Conference Paper

References (27)

1. K. I. Farkas, N. P. Jouppi, and P. Chow, “How Useful Are Non-Blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?” Technical Report WRL RR 94/8, Western Research Laboratory – Compaq, Palo Alto, CA, August 1994.
2. J. Pierce and T. Mudge, “The effect of speculative execution on cache performance,” IPPS 94, Int. Parallel Processing Symp., Cancun Mexico, pp. 172-179, Apr. 1994.
3. G. Reinman, T. Austin, and B. Calder, “A Scalable Front-End Architecture for Fast Instruction Delivery,” 26th International Symposium on Computer Architecture, pages 234-245, May 1999.
4. S. Wallace, D. Tullsen, and B. Calder, “Instruction Recycling on a Multiple-Path Processor,” 5th International Symposium On High Performance Computer Architecture, pages 44-53, January 1999.
5. G. Reinman and B. Calder, “Predictive Techniques for Aggressive Load Speculation,” 31st International Symposium on Microarchitecture, pages 127-137, December 1998.
6. J. D. Collins, H. Wang, D. M. Tullsen, C. Hughes, Y.-F. Lee, D. Lavery, J. P. Shen, “Speculative Precomputation: Long-range Prefetching of Delinquent Loads,” In 28th International Symposium on Computer Architecture, July, 2001.
7. J. Dundas and T. Mudge, “Improving data cache performance by pre-executing instructions under a cache miss,” Proc. 1997 ACM Int. Conf. on Supercomputing, July 1997, pp. 68-75.
8. A.J. Smith, “Cache Memories,” Computing Surveys, Vol. 14, No. 3, Sept. 1982, pp. 473-530.
9. N.P. Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-associative Cache and Prefetch Buffers,” Proc. 17th Annual International Symposium on Computer Architecture, Seattle, WA, May 1990, pp. 364-373.
10. F. Dahlgren, M. Dubois and P. Stenstrom, “Fixed and Adaptive Sequential Prefetching in Shared-memory Multiprocessors,” Proc. First IEEE Symposium on High Performance Computer Architecture, Raleigh, NC, Jan. 1995, pp. 68-77.
11. T.F. Chen and J.L Baer, “Effective Hardware-Based Data Prefetching for High Performance Processors,” IEEE Transactions on Computers, Vol. 44, No.5, May 1995, pp. 609-623.
12. D. Joseph and D. Grunwald, “Prefetching using markov predictors,” IEEE Transactions on Computers, Vol. 48, No 2, 1999, pp 121-133.
13. G. Reinman, B. Calder, and T. Austin, “Fetch Directed Instruction Prefetching,” In proceedings of the 32nd International Symposium on Microarchitecture, November 1999.
14. T.F. Chen and J.L Baer, “A Performance Study of Software and Hardware Data Prefetching Schemes,” Proc. of the 21st Annual International Symposium on Computer Architecture, Chicago, Il, April 1994, pp. 223-234.
15. R. Pendse and H. Katta, “Selective Prefetching: Prefetching when only required,” Proc. of the 42nd IEEE Midwest Symposium on Circuits and Sysstems, volume 2, 2000, pp. 866-869.
16. C-K. Luk and T. C. Mowry. “Compiler-based prefetching for recursive data structures,” In Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222--233, Oct. 1996.
17. Bernstein, D., C. Doron and A. Freund, “Compiler Techniques for Data Prefetching on the PowerPC,” Proc. International Conf. on Parallel Architectures and Compilation Techniques, June 1995, pp. 19-26.
18. E.H. Gornish, E.D. Granston and A.V. Veidenbaum, “Compiler-directed Data Prefetching in Multiprocessors with Memory Hierarchies,” Proc. 1990 International Conference on Supercomputing, Amsterdam, Netherlands, June 1990, pp. 354-368.
19. M.H. Lipasti, W.J. Schmidt, S.R. Kunkel and R.R. Roediger, “SPAID: Software Prefetching in Pointer and Call-Intensive Environments,” Proc. 28th Annual International Symposium on Microarchitecture, Ann Arbor, MI, November 1995, pp. 231-236.
20. J. Pierce and T. Mudge, “Wrong-Path Instruction Prefetching,” Proc. of 29th Annual IEEE/ACM Symp. Microarchitecture (MICRO-29), Dec. 1996, pp. 165-175.
21. S. P. VanderWiel and D. J. Lilja, “Data Prefetch Mechanisms,” ACM Computing Surveys, Vol. 32, Issue 2, June 2000, pp. 174-199.
22. D.C. Burger, T.M. Austin, and S. Bennett, “Evaluating future Microprocessors: The SimpleScalar Tool Set,” Technical Report CS-TR-96-1308, University of Wisconsin- Madison, July 1996.
23. AJ KleinOsowski, J. Flynn, N. Meares, and D. J. Lilja, “Adapting the SPEC 2000 Benchmark Suite for Simulation-Based Computer Architecture Research,” Workload Characterization of Emerging Computer Applications, L. Kurian John and A. M. Grizzaffi Maynard (eds.), Kluwer Academic Publishers, pp 83-100, (2001).
24. S-T Pan, K. So, and J.T. Rahmeh, “Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation,” Proc. of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, 1992, pp. 76-84.
25. T.Y. Yeh and Y. N. Patt, “A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History,” Proc. of the International Symposium on Computer Architecture, 1993, pp. 257-267.
26. R. Sendag, D. J. Lilja, and S. R. Kunkel, “Exploiting the Prefetching Effect provided by Executing Misprediced Load Instructions,” Laboratory for Advanced Research in Computing Technology and Compilers, Technical Report No. ARCTIC 02-05, May 2002.
27. D. A. Patterson and J. L. Hennessy: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann press, 1995, pp. 393-395.