A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 226-234

  Haynes, S D ^a   Cheung, P Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; IMAGE PROCESSING; RECONFIGURABLE HARDWARE; VIDEO SIGNAL PROCESSING;

BINARY MULTIPLICATION; FLEXIBLE ARRAYS; RECONFIGURABLE; VIDEO IMAGE PROCESSING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84956866497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707900     Document Type: Conference Paper

References (8)

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