Silicon-on-insulator "gate-all-around" MOS device

1990 IEEE SOS/SOI Technology Conference, Proceedings

Volumn , Issue , 1990, Pages 137-138

  Colinge, J P ^a   Gao, M H ^a   Romano, A ^a   Maes, H ^a   Claeys, C ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

HARDNESS; MOTIVATION; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SYSTEMS ENGINEERING;

DOUBLE-GATE DEVICE; GATE-ALL-AROUND; PLANAR PROCESS; RADIATION HARDNESS; SHORT CHANNELS; THICKNESS OF THE OXIDE LAYERS; TOTAL DOSE RADIATION HARDNESS; VERTICAL DEVICES;

MOS DEVICES;

EID: 84956267300     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOSSOI.1990.145749     Document Type: Conference Paper

References (3)

1. F. Balestra et al., IEEE Electron Device Letters, Vol. 8, p. 410, 1987
2. D. Hisamoto et al., Techn. Digest IEDM, p. 833, 1989
3. J. C. Sturm et al., IEEE Electron Device Lett., Vol. 9, p. 460, 1988