Implementation of a gate-level evolvable hardware chip

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2210, Issue , 2001, Pages 38-49

  Iwata, Masaya ^a   Kajitani, Isamu ^a   Liu, Yong ^b   Kajihara, Nobuki ^c   Higuchi, Tetsuya ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b UNIVERSITY OF AIZU   (Japan)

^c NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; GENETIC ALGORITHMS;

CIRCUIT STRUCTURES; CONTROL LOGIC; EVOLVABLE HARDWARE; GATE LEVELS; GENETIC LEARNING; LARGE SYSTEM; LEARNING SPEED; LSI CHIPS;

RECONFIGURABLE HARDWARE;

EID: 84955620531     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45443-8_4     Document Type: Conference Paper

References (11)

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