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Volumn 2210, Issue , 2001, Pages 50-61
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A VLSI implementation of an analog neural network suited for genetic algorithms
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Author keywords
[No Author keywords available]
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Indexed keywords
GENETIC ALGORITHMS;
NETWORK ARCHITECTURE;
VLSI CIRCUITS;
ANALOG NEURAL NETWORK;
FULL-SPEED;
MULTI-LAYERED;
SILICON AREA;
VLSI IMPLEMENTATION;
NETWORK LAYERS;
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EID: 84955596039
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/3-540-45443-8_5 Document Type: Conference Paper |
Times cited : (9)
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References (7)
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