Cautious, Machine-Independent performance tuning for shared-memory multiprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1123, Issue , 1996, Pages 106-113

  Talbot, Sarah A M ^a   Bennett, Andrew J ^a   Kelly, Paul H J ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; USER EXPERIENCE;

MANUAL TUNING; MEMORY SYSTEMS; PERFORMANCE TUNING; SHARED MEMORY ARCHITECTURE; SHARED MEMORY MULTIPROCESSOR;

MEMORY ARCHITECTURE;

EID: 84955558691     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61626-8_13     Document Type: Conference Paper

References (6)

1. Mats Brorsson. SM-prof: A tool to visualise and find cache coherence performance bottlenecks in multiprocessor programs. In Proceedings of the A CM SIGMETRICS and Performance '95, pages 178-187, May 1995.
2. Susan J. Eggers and Randy H. Katz. A characterisation of sharing in parallel programs and its application to coherency protocol evaluation. 15th Annual International Symposium on Computer Architecture, Honolulu, May, in Computer Architecture News, 16(2):373-382, May 1988.
3. M. Martonosi, A. Gupta, and T. Anderson. Tuning memory performance of sequentim and parallel programs. IEEE Computer, 28(4):32-40, April 1995.
4. Jaswinder Pal Singh, Wolf-Dietrich Weber, and Anoop Gupta. SPLASH: Stanford parallel applications for shared-memory. Computer Architecture News, 20(1):5-44, March 1992.
5. Sarah A. M. Talbot. Performance tuning of programs for shared-memory multiprocessors. Master's thesis, Department of Computing, Imperial College, London, U.K., 1995.
6. B. A. Tanyi. Iterative Solution off the Incompressible Navier-Stokes Equations on a Distributed Memory Parallel Computer. PhD thesis, UMIST, 1993.