The RR/RR CICQ switch: Hardware design for 10-Gbps link speed

IEEE International Performance, Computing and Communications Conference, Proceedings

Volumn , Issue , 2003, Pages 481-485

  Yoshigoe, Kenji ^a   Christensen, Ken ^a   Jacob, Aju ^b  

^a University of South Florida   (United States)

^b University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONGESTION CONTROL (COMMUNICATION); FEEDBACK; FIELD PROGRAMMABLE GATE ARRAYS; QUEUEING NETWORKS; SIGNAL ENCODING; TELECOMMUNICATION LINKS; DESIGN; ELECTRIC SWITCHES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH SPEED NETWORKS; RECONFIGURABLE HARDWARE;

COMBINED INPUT AND CROSSBAR QUEUED SWITCH; FEEDBACK MASKING;

SWITCHING SYSTEMS; INTEGRATED CIRCUIT DESIGN;

CICQ SWITCHES; ESTIMATED COSTS; FPGA IMPLEMENTATIONS; HARDWARE DESIGN; INPUT BUFFERED SWITCH; LINK SPEED; PRIORITY ENCODER;

EID: 84954433017     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. T. Anderson, S. Owicki, J. Saxe, and C. Thacker, "High-Speed Switch Scheduling for Local-Area Networks," ACM Transactions on Computer Systems, Vol. 11, No. 4, pp. 319-352, November 1993.
2. AVNET Inc, "Designing High-Performance Systems with Virtex-II Pro FPGA Devices," Presentation for the Florida Suncoast IEEE chapter, September 10, 2002.
3. Cisco Systems, "Data sheet: Cisco 12416 Internet Router," URL: http://www.cisco.com/warp/public/cc/pd/rt/12000/12416/prodlit/itro_ds.htm.
4. J. Delgado-Frias and J. Nyathi, "A VLSI High-Performance Encoder with Priority Lookahead," Proceedings of the 8th Great Lakes Symposium on VLSI, pp.59-64, February 1998.
5. P. Gupta and N. McKeown, "Design and Implementation of a Fast Crossbar Scheduler," IEEE Micro, Vol. 19, No. 1, January/February 1999.
6. Intel Corp., "Intel Accelerates 10-Gigabit Communications In Enterprise Data Centers With New XPAK Optical Transceiver," Press Release, URL: http://www.intel.com/pressroom/archive/releases/20020827net.htm.
7. T. Javadi, R. Magill, and T. Hrabik, "A High-Throughput Scheduling Algorithm for a Buffered Crossbar Switch Fabric," Proceedings of IEEE 2001 International Conference on Communications, pp. 1581-1591, June 2001.
8. N. McKeown, "The iSLIP Scheduling Algorithm for Input-Queued Switches," IEEE/ACM Transactions on Networking, Vol. 7, No. 2, pp. 188-201, April 1999.
9. M. Nabeshima, "Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch," IEICE Transactions on Communications, Vol. E83-B, No. 3, pp. 737-741, March 2000.
10. NuHorizons Electronic Corp., "XC2VP Virtex-II Pro FPGA," URL: http://www.nuhorizons.com/products/NewProducts/POQ13/xilinx.html.
11. A. Mekkittikul and N. McKeown, "A Starvation-free Algorithm for Achieving 100% Throughput in an Input-Queued Switch," IEEE Transactions on Communications, Vol. 47, No. 8, pp. 1260-1267, August 1999.
12. R. Rojas-Cessa, E. Oki, Z. Jing, and H. Chao, "CIXB-1: Combined Input-One-Cell Crosspoint Buffered Switch," Proceedings of the 2001 IEEE Workshop on High Performance Switching and Routing, pp. 324-329, May 2001.
13. V. Singhal and R. Le, "High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices," Xilinx Appliction Note XAPP240 (v1.0), March 14, 2000. URL: http://www.Xilinx.com/xapp/xapp240.pdf.
14. D. Stephens and H. Zhang, "Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture," Proceedings of IEEE INFOCOM, pp. 282-290, April 1998.
15. Xilinx Inc., "10-Gigabit Ethernet MAC with XGMII or XAUI v2.1 DS201 (v2.1)," June 24, 2002 URL: http://www.xilin.com/ipcenter/catalog/logicore/docs/ten_gig_eth_mac.pdf.
16. Xilinx Inc, "Xilinx Vertex II Pro Platform FPGA Data Sheet DS083-1 (v2.1)", September 3, 2002. URL: http://www.Xilinx.com/publications/products/v2pro/ds_pdf/ds083.htm.
17. Xilinx Inc., "Xilinx WebPACK 4.2," URL: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack.
18. K. Yoshigoe and K. Christensen, "A Parallel-Polled Virtual Output Queued Switch with a Buffered Crossbar," Proceedings of the 2001 IEEE Workshop on High Performance Switching and Routing, pp. 271-275, May 2001.