Low temperature CMOS self-aligned poly-Si TFTs and circuit scheme utilizing new ion doping and masking technique

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1991-January, Issue , 1991, Pages 555-558

  Inoue, Satoshi ^a   Matsuo, Minoru ^a   Hashizume, Tsutomu ^a   Ishiguro, Hideto ^a   Nakazawa, Takashi ^a   Ohshima, Hiroyuki ^a  

^a SEIKO EPSON CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRYSTAL IMPURITIES; ELECTRON DEVICES; GLASS; ION IMPLANTATION; IONS; LIQUID CRYSTAL DISPLAYS; OSCILLATORS (ELECTRONIC); POLYCRYSTALLINE MATERIALS; RECONFIGURABLE HARDWARE; SEMICONDUCTOR DOPING; SHIFT REGISTERS; SUBSTRATES; TEMPERATURE;

ACCELERATING VOLTAGES; CIRCUIT FUNCTIONALITY; INTEGRATED DRIVER; LOW TEMPERATURE CMOS; MASKING TECHNIQUE; POLYCRYSTALLINE SILICON THIN-FILM TRANSISTOR; SELF ALIGNED STRUCTURE; SOURCE AND DRAINS;

THIN FILM TRANSISTORS;

EID: 84954158104     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1991.235409     Document Type: Conference Paper

References (0)