Low temperature sintering process for deposition of nano-structured metal for nano IC packaging

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 551-556

  Kwan, Wong Wai ^a   Kripesh, V ^a   Iyer, M K ^a   Gupta, M ^b   Tay, A A O ^b   Tummala, R ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; METALS; MICROELECTRONICS; NANOSTRUCTURES; POWDER METALS; POWDERS; REDUCING AGENTS; SINTERING; TEMPERATURE;

IC PACKAGING; LOW-TEMPERATURE SINTERING; METALLIC POWDER; NANO POWDERS; NANO-STRUCTURED; ORGANIC CARRIERS; SINTERING TEMPERATURES; SURFACE TREATED;

SILICON WAFERS;

EID: 84954049396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271582     Document Type: Conference Paper

References (8)

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