Ultra-high density board technology for sub-100 μm pitch nano-wafer level packaging

Proceedings of 5th Electronics Packaging Technology Conference, EPTC 2003

Volumn , Issue , 2003, Pages 125-129

  Sundaram, V ^a   Liu, Fuhan ^a   Aggarwal, A O ^a   Hosseini, S M ^a   Mekala, S ^a   White, G E ^a   Tummala, R R ^a   Swaminathan, M ^a   Kim, Woopoung ^a   Madhavan, R ^a   Lo, G ^a   Iyer, M K ^b   Vaidyanathan, K ^b   Wong, Ee Hua ^b   Rajoo, Ranjan ^b   Chong, C T ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT INTERCONNECTS; LITHOGRAPHY; PRINTED CIRCUIT BOARDS; SUBSTRATES;

ELECTRICAL PERFORMANCE; FABRICATION PROCESS; HIGH-SPEED SIGNALS; INTERCONNECTION DENSITY; NANO-WAFER LEVEL PACKAGING; STATE OF THE ART; THIN-FILM DIELECTRICS; ULTRAHIGH DENSITY;

ELECTRONICS PACKAGING;

EID: 84954046093     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1271502     Document Type: Conference Paper

References (6)

1. The 2001 International Technology Roadmap for Semiconductors: Technology Needs, Flip Chip Board Fan-out Requirements. Semiconductor Industry Association (SIA), 2002 Update.
2. National Electronics Manufacturing Initiative (NEMI) Roadmap, 2000.
3. Rao R. Tummala, et. al., Invited Talk, "SOP vs. SOC at Georgia Tech PRC", pp.1-8, Proceedings of the International Conference on Electronics Packaging, April 18-20, 2001, Tokyo, Japan.
4. D. J. Alcoe, M. A. Jimarez, G. W. Jones, T. E. Kindl, J. S. Kresge, J. P. Libous, R. J. Stutzman, and Cheryl L. Tytran-Palomaki, "HyperBGA™: a High Performance, Low Stress, Laminate Ball Grid Array Flip Chip Carrier", MicroNews, Second Quarter 2000, Vol. 6, No. 2, pp. 27-36.
5. nd ECTC Conference, New Orleans, USA, May 2003.
6. "Ceramic Matrix Composite Boards for SOP and SIP Electronic Packaging", NIST 2002 ATP Award, Starfire Systems, NY, www.atp.nist.gov.