A high-speed multi-dielectric capacitance-extraction algorithm for MCM interconnects

Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92

Volumn , Issue , 1992, Pages 86-89

  Le Coz, Y L ^a   Iverson, R B ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; EXTRACTION; MICROPROCESSOR CHIPS; MULTICHIP MODULES; PERSONAL COMPUTERS; STOCHASTIC SYSTEMS;

CAPACITANCE EXTRACTION; COMPUTATIONAL RESULTS; DIELECTRIC CAPACITANCE; DIELECTRIC INTERFACE; ELECTRIC PERMITTIVITIES; STATISTICAL ERRORS; STOCHASTIC ALGORITHMS; TWO-DIMENSIONAL CROSS SECTIONS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84953103021     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MCMC.1992.201454     Document Type: Conference Paper

References (3)

1. Y. L. Le Coz and R. B. Iverson, "A High-Speed Capacitance Extraction Algorithm for Multi-Level VLSI Interconnects", Proc. of the 8th International IEEE VMIC, 1991, p. 364.
2. Y. L. Le Coz and R. B. Iverson, "A Stochastic Algorithm for High-Speed Capacitance Extraction in Integrated Circuits", Solid-St. Electron., accepted for publication, 1991.
3. C. S. Walker, Capacitance, Inductance, and Crosstalk Analysis, Artech House, Boston, 1990, pp. 48-51.