Exposing data-level parallelism in sequential image processing algorithms

Proceedings - Working Conference on Reverse Engineering, WCRE

Volumn 2002-January, Issue , 2002, Pages 245-254

  Baumstark, Lewis ^a   Wills, Linda ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Concurrent computing; Discrete cosine transforms; Filtering algorithms; Image processing; Parallel architectures; Parallel processing; Pixel; Power engineering computing; Programming profession; Signal processing algorithms

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER AIDED ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; COSINE TRANSFORMS; DATA FLOW ANALYSIS; DISCRETE COSINE TRANSFORMS; IMAGE MATCHING; MATLAB; PARALLEL ARCHITECTURES; PATTERN MATCHING; PIXELS; PROFESSIONAL ASPECTS; REVERSE ENGINEERING; SIGNAL FILTERING AND PREDICTION; SIGNAL PROCESSING;

CONCURRENT COMPUTING; FILTERING ALGORITHM; PARALLEL PROCESSING; POWER ENGINEERING COMPUTING; PROGRAMMING PROFESSION; SIGNAL PROCESSING ALGORITHMS;

IMAGE PROCESSING;

EID: 84952917156     PISSN: 10951350     EISSN: None     Source Type: Journal    
DOI: 10.1109/WCRE.2002.1173082     Document Type: Article

References (23)

1. R. Gonzalez and R. Woods, Digital Image Processing, Addison-Wesley, 1993.
2. D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publishers, Inc., 1997.
3. J. R. Allen and K. Kennedy, Automatic Translation of FORTRAN Programs to Vector Form, TOPLAS, 9:4, pp. 491-542, Oct.1987.
4. D. DeVries, A Vectorizing SUIF Compiler: Implementation and Performance. Master's thesis, University of Toronto, June 1997.
5. D. Kuck, et al., Analysis and transformation of programs for parallel computation, computation. In COMPSAC 80, pp. 709-715, Chicago, IL, October 1980.
6. R. Wilson, et al., SUIF: an infrastructure for research on parallelizing and optimizing compilers, SIGPLAN Notices, 29(12), pp. 31-37, Dec. 1994.
7. K. McKinley, "Automatic and Interactive Parallelization," Rice University, Houston, Texas, CRPC-TR92214-S, March 1994.
8. D. Kulkarni, M. Stumm, "Linear Loop Transformations in Optimizing Compilers for Parallel Machines," The Australian Computer Journal, May 1995, pp. 41-50.
9. C. Lee and D. DeVries, Initial Results on the Performance and Cost of Vector Microprocessors, Proc. of 30th Annual Int. Symposium on Microarchitecture, pp. 171-182, Research Triangle Park, NC, Dec. 1997.
10. D. Callahan, et al., "Vectorizing compilers: a test suite and results," Proc. Supercomputing '88, pp. 98-105, Nov. 1988.
11. B. Di Martino, H. P. Zima, "Support of automatic parallelization with concept comprehension," Journal of Systems Architecture, 45(6-7):pp. 427-439, 1999.
12. Christoph W. Kessler, "The PARAMAT Project: Current Status and Plans for the Future," in Proc. of AP'95 Workshop on Automatic Data Layout and Performance Prediction, Rice University, Houston, April 1995.
13. B. Di Martino, C. W. Kessler, "Two Program Comprehension Tools for Automatic Parallelization," IEEE Concurrency, vol. 8, no. 1, January-March 2000, pp. 37-59.
14. Christoph W. Kessler, "Pattern-Driven Automatic Parallelization," Scientific Programming, vol. 5, no. 3, Fall 1996, pp. 251-274R.
15. R. Metzger, "Automated Recognition of Parallel Algorithms in Scientific Applications," in Proc. of Workshop on Plan Recognition at IJCAI'95, August 1995.
16. V. Gustin, T. M. Pinkston, "Extracting SIMD parallelism from 'for' loops," ICPP, Valencia, Spain, Sept. 2001, pp. 23-28.
17. G. A. Baxes, Digital Image Processing: Principles And Applications, NY: John Wiley & Sons, Inc., 1994, pp. 86-99.
18. H. H. Cat, et al., "SIMPil: An OE Integrated SIMD Architecture for Focal Plane Processing Applications," Proc. 3rd International Conference on Massively Parallel Processing using Optical Interconnections, Maui, 1996, pp. 44-52.
19. TMS320C62x Image/Video Processing Library Programmer's Reference, Texas Instruments Literature Number SPRU400, March 2000, pp. 5-36-5-38.
20. S. Sander, "Retargetable Compilation for Variable-Grain Data Parallel Execution in Image Processing," Georgia Tech Ph.D. thesis, August 2002.
21. A. Peleg and U. Weiser, "MMX Technology Extension to the Intel Architecture," IEEE Micro, Vol. 16, No. 4, pp. 5159, Aug. 1996.
22. M. Phillip et al, "AltiVec Technology: Accelerating Media Processing Across the Spectrum," Proc. of the HOTCHIPS-X Conference, Aug. 1998.
23. S. Oberman et al, "AMD 3DNow! Technology and the K6-2 Microprocessor," Proc. of HOTCHIPS-X Conference, 1998.