Precise exceptions in asynchronous processors

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 16-28

  Manohar, R ^b   Nystrom M ^a   Martin, A J ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b Cornell University ^*  (United States)

Author keywords

Algorithms; Computer architecture; Computer science; Costs; Floating point arithmetic; Hardware; Laboratories; Modems; Operating systems; Software performance

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER SCIENCE; COSTS; DIGITAL ARITHMETIC; LABORATORIES; MODEMS;

ASYNCHRONOUS PROCESSORS; EXCEPTION HANDLING MECHANISM; IMPLEMENTATION STRATEGIES; INSTRUCTION FETCH; PROCESSOR ARCHITECTURES; SOFTWARE COMPLEXITY; SOFTWARE PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 84951816842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915547     Document Type: Conference Paper

References (8)

1. S.B. Furber, P. Day, J.D. Garside, N.C. Paver, and J.V. Woods. A micropipelined ARM. Proceedings of the VII Banff Workshop: Asynchronous Hardware Design, August 1993.
2. C.A.R. Hoare. Communicating Sequential Processes. Communications of the ACM, 21(8):666-677, 1978
3. Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, CS-TR-98-12, California Institute of Technology, July 1998.
4. Alain J. Martin. Compiling Communicating Processes into Delay-insensitive VLSI circuits. Distributed Computing, 1(4), 1986.
5. A.J. Martin, A. Lines, R. Manohar, M. Nyström, P. Penzes, R. Southworth, U. Cummings, and T.K. Lee. The Design of an Asynchronous MIPS R3000 Processor. Proceedings of the 17th Conference on Advanced Research in VLSI. Los Alamitos, Calif.: IEEE Computer Society Press, 1997.
6. Alain J. Martin, Steven M. Burns, Tak-Kwan Lee, Drazen Borkovic, and Pieter J. Hazewindus. The design of an asynchronous microprocessor. In Charles L. Seitz, editor, Advanced Research in VLSI: Proceedings of the Decennial Caltech Conference on VLSI, pp. 351-373, MIT Press, 1991.
7. William F. Richardson. Architectural Considerations in a Self-Timed Processor Design. Ph.D. thesis, Department of Computer Science, University of Utah, 1996.
8. Ken Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28-40, April 1996.