Analysis of a multi-layer fault-tolerant COTS architecture for deep space missions

Proceedings - 3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology

Volumn , Issue , 2000, Pages 70-76

  Chau, S N ^a   Alkalai, L ^a   Tai, A T ^b  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b IA Tech Inc ^*  (United States)

Author keywords

Aerospace electronics; Costs; Design methodology; Fault tolerance; Fault tolerant systems; Laboratories; Logic; Mission critical systems; Propulsion; Protection

Indexed keywords

COMPUTER CIRCUITS; COSTS; DESIGN; FIGHTER AIRCRAFT; IEEE STANDARDS; INTERPLANETARY FLIGHT; NASA; PROPULSION;

AEROSPACE ELECTRONICS; COMMERCIAL OFF THE SHELVES; COMMERCIAL OFF-THE SHELVES; COMMERCIAL-OFF-THE-SHELF; DESIGN METHODOLOGY; FAULT- TOLERANT SYSTEMS; LOGIC; MISSION CRITICAL SYSTEMS; MULTI-LAYERS; PROTECTION;

FAULT TOLERANCE;

EID: 84951733646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSET.2000.888035     Document Type: Conference Paper

References (11)

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