An FPGA implementation of triangle mesh decompression

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 22-34

  Mitra, Tulika ^a   Chiueh, Tzi Cker ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b Stony Brook University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; ENCODING (SYMBOLS); HARDWARE; MESH GENERATION;

3D GEOMETRIC MODEL; BANDWIDTH REQUIREMENT; COMPRESSION EFFICIENCY; DECOMPRESSION ALGORITHM; DESIGN AND IMPLEMENTATIONS; FPGA IMPLEMENTATIONS; HARDWARE IMPLEMENTATIONS; THREEDIMENSIONAL (3-D);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84950113383     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2002.1106658     Document Type: Conference Paper

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