FDRA: A software-pipelining algorithm for embedded VLIW processors

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 34-40

  Akturan, C ^a   Jacome, M F ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Constraint optimization; Delay; Finite impulse response filter; Pipeline processing; Processor scheduling; Scheduling algorithm; Software algorithms; VLIW

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); CONSTRAINED OPTIMIZATION; ECONOMIC AND SOCIAL EFFECTS; EMBEDDED SYSTEMS; FIR FILTERS; FLOW MEASUREMENT; IMPULSE RESPONSE; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PIPELINES; PROGRAM COMPILERS; SCHEDULING ALGORITHMS; SYNTHESIS (CHEMICAL);

CONSTRAINT OPTIMIZATIONS; DELAY; PIPELINE PROCESSING; PROCESSOR SCHEDULING; SOFTWARE ALGORITHMS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84949976548     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874026     Document Type: Conference Paper

References (15)

1. M. Lam, "A systolic array optimizing compiler", Ph.D. Thesis, Carnegie Mellon University, 1987.
2. M. Lam, Software Pipelining, "An Effective Scheduling Technique for VLIW Machines", Proceedings of the SIGPLAN 1988, Conf. on Programming Language Design and Implementation, Atlanta, Georgia, June 22-24, 1988.
3. C. E. Leiserson and J. B. Saxe, "Optimizing Synchronous Circuitry and Retiming", Proceedings of the 3rd Caltech Conference on VLSI, pages 5-35, 1983.
4. C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry", Algorithmica, pages 5-35, 1991.
5. B.R. Rau, C. D. Gleaser, "Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing", Proceedings of 14th Annual Workshop on Microprogramming, October 1981, pages 183-198.
6. T. C. Denk, K. K. Parhi, "Exhaustive Scheduling and Retiming of Digital Signal Processing Systems", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, pages 821-837, Vol. 45, No. 7, July 1998.
7. E. M. Reingold, J.Nievergelt, N. Deo, "Combinatorial Algorithms: Theory and Practice", Englewood Cliffs, New Jersey: Prectice-Hall Inc., 1977.
8. P. G. Paulin, J. P. Knight, "Force Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Transactions on Computer-Aided Design, Vol. 8, No. 6 June 1989.
9. L. Chao, A. LaPaugh, E.H. Sha, "Rotation Scheduling: A loop Pipelining Algorithm", IEEE Transactions on Computer Aided Design", Vol. 16, No. 3, March 1997, pp. 229-239.
10. C. Wang, K. K. Parhi, "High Level DSP Synthesis Using MARS Design System", Proceedings of the International Symposium on Circuits and Systems, pages 164-167, 1992.
11. T. Lee, A. C. Wu, D. D. Gajski, Y. Lin, "An effective methodology for functional pipelining", Proceedings of the International Conference on Computer Aided Design, pages 230-233, Dec 1992.
12. G. Goossens, J. Vandewalle, H. De Man, "Loop optimization in register-transfer scheduling for DSP-systems", Proceedings of the ACM/IEEE Design Automation Conference, pages 826-831, 1989.
13. A. Aiken, A. Nicolau, S. Novack, "Resource-Constrainted Software Pipelining", IEEE Transactions on Parallel and Distributed Systems Vol.6, No. 12, Dec.er 1995.
14. M. Potkonjak, J. Rabaey, "Retiming For Scheduling", VLSI Signal Processing IV, pages 23-32, Nov 1990.
15. M. F. Jacome, G. de Veciana and C. Akturan, "Resource Constrained Dataflow Retiming Heuristics for VLIW ASIPs", Proceedings of IEEE/ACM 7th International Workshop on Hardware/Software Codesign (CODES'99), Apr 99.