Intervals in software execution cost analysis

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 130-135

  Wolf, F ^a   Ernst, R ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

Computer architecture; Context; Costs; Embedded system; Energy consumption; Flow graphs; Process control; Timing; Upper bound; Wireless communication

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CONTROL SYSTEMS; COSTS; EMBEDDED SYSTEMS; ENERGY UTILIZATION; FLOW GRAPHS; PROCESS CONTROL; SYNTHESIS (CHEMICAL); WIRELESS TELECOMMUNICATION SYSTEMS;

CONTEXT; EXECUTION CONTEXT; PROGRAM PROPERTIES; SOFTWARE EXECUTION; TARGET ARCHITECTURES; TIMING; UPPER BOUND; WIRELESS COMMUNICATIONS;

COST BENEFIT ANALYSIS;

EID: 84949933049     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874039     Document Type: Conference Paper

References (14)

1. A. V. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading, GB, 1988.
2. T. M. Conte and C. E. Gimarc. Fast Simulation of Computer Architectures. Kluwer Academic Publishers, 1995.
3. A. Doboli, J. Hallberg, and P. Eles. A simulation model for the OAM functionality in ATM switches. Technical report, Linköping, 1995.
4. C. Ferdinand and R. Wilhelm. On predicting data cache behavior for real-time systems. In Proceedings of Language, Compilers and Tools for Embedded Systems, 1998.
5. J. Gong, D. Gajski, and S. Narayan. Software execution from executable specification. The Journal of Computer and Software Engineering, pages 239-258, 1994.
6. J. Gustafsson and A. Ermedahl. Automatic derivation of path and loop annotations in object-oriented real-time programs. Journal of Parallel and Distributed Computing Practices, 1998.
7. Y.-T. S. Li and S. Malik. Performance Analysis of Real-Time Embedded Software. Kluwer Academic Publishers, 1999.
8. J. Montanaro. A 160-MHz, 32-b, 0.5W CMOS RISC microprocessor. IEEE Journal of Solid State Circuits, pages 1703-1714, Nov. 1996.
9. C. Y. Park and A. C. Shaw. Experiments with a program timing tool based on source-level timing scheme. In Proceedings of Real-Time System Symposium, pages 72-81, 1990.
10. P. Puschner and C. Koza. Calculating the maximum execution time of real-time programs. Journal of Real-Time Systems, 1(2):160-176, 1989.
11. V. Tiwari, S. Malik, and A. Wolfe. Instruction level power analysis and optimisation of software. VLSI Signal Processing, pages 1-18, 1996.
12. F. Wolf and R. Ernst. Execution cost interval refinement in static software analysis. Technical report, Technical University of Braunschweig, 2000.
13. W. Ye and R. Ernst. Embedded program timing analysis based on path clustering and architecture classification. In Proceedings International Conference on Computer-Aided Design (ICCAD '97), pages 598-604, San Jose, USA, 1997.
14. D. Ziegenbein, R. Ernst, K. Richter, J. Teich, and L. Thiele. Combining multiple models of computation for scheduling and allocation. In Sixth international Workshop on Hardware/Software Co-Design, pages 9-13, Seattle, 1998.