A communication scheduling algorithm for multi-FPGA systems

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 299-300

  Suh, Jinwoo ^a   Kang, Dong In ^a   Crago, Stephen P ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTIMIZATION; PROBLEM SOLVING;

COMMUNICATION SCHEDULING; EFFICIENT COMMUNICATIONS; MULTI-FPGA SYSTEM; NP COMPLETE; OPTIMAL ALGORITHM; OPTIMAL SCHEDULING ALGORITHM; ORDERS OF MAGNITUDE; PROBLEM INSTANCES;

SCHEDULING ALGORITHMS;

EID: 84949813877     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903425     Document Type: Conference Paper

References (2)

1. J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulations", FCCM'93, April 3y1993.
2. M. R. Garey, D. S. Johnson, and R. Sethi, "The Complexity of Flowshop and Jobshop Scheduling", Mathematics of Operations Research, Vol. 1, No. 2, May 1976.