Pattern recognition and reconstruction on a FPGA coprocessor board

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 2000, Pages 325-326

  Manner R ^a   Sessler, M ^a   Simmler, H ^a  

^a UNIVERSITY OF MANNHEIM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

CUSTOM COMPUTING MACHINES; DEGREE OF PARALLELISM; DETECTOR SYSTEMS; FAST PATTERN RECOGNITION; FILTER ALGORITHM; HIGH-ENERGY ACCELERATOR; RECOGNITION AND RECONSTRUCTION; THREE DIMENSIONAL IMAGES;

PATTERN RECOGNITION;

EID: 84949806561     PISSN: 10823409     EISSN: None     Source Type: Journal    
DOI: 10.1109/FPGA.2000.903438     Document Type: Article

References (3)

1. 50kHz Pattern Recognition on the Large FPGA Processor Enable++, A. Kugel et.al., IEEE Symposium on FP-GAs for CCMs, Page 262-263, April 1998.
2. Enable++: A Second Generation FPGA Processor, H. Högl et.al., IEEE Symposium on FPGAs for CCMs, Page 45-53, April 1995.
3. Global Pattern Recognition in the TRT for B-Physics in the ATLAS Trigger, J. Baines, et.al., ATL-DAQ-99-012, 21 September 1999.