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Volumn 2000-January, Issue , 2000, Pages 77-79

Simulation strategy after model checking: Experience in industrial SOC design

Author keywords

Assembly; Computer bugs; Control systems; Electronic mail; Electronics industry; Fabrication; Industrial electronics; Large scale integration; Reduced order systems; System testing

Indexed keywords

ASSEMBLY; COMPUTER CONTROL SYSTEMS; CONTROL SYSTEMS; ELECTRONIC MAIL; ELECTRONICS INDUSTRY; FABRICATION; INDUSTRIAL ELECTRONICS; INTEGRATION TESTING; LSI CIRCUITS; MICROPROCESSOR CHIPS; PROGRAM DEBUGGING;

EID: 84949646883     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889563     Document Type: Conference Paper
Times cited : (2)

References (8)
  • 1
    • 0028135832 scopus 로고
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    • B. Chen, M. Yamazaki, and M. Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking," in ED&TC, pp. 132-136, 1994.
    • (1994) ED&TC , pp. 132-136
    • Chen, B.1    Yamazaki, M.2    Fujita, M.3
  • 2
    • 0029213725 scopus 로고
    • Model Checking in Industrial Hardware Design
    • J. Bormann, J. Lohse, M. Payer, and G. Venzl, "Model Checking in Industrial Hardware Design," in 32nd DAC, pp. 298-303, 1995.
    • (1995) 32nd DAC , pp. 298-303
    • Bormann, J.1    Lohse, J.2    Payer, M.3    Venzl, G.4
  • 3
    • 0032289911 scopus 로고    scopus 로고
    • Model Checking of a Real ATM Switch
    • J. Lu, S. Tahar, D. Voicu, and X. Song, "Model Checking of a Real ATM Switch," in ICCD, pp. 195-198, 1998.
    • (1998) ICCD , pp. 195-198
    • Lu, J.1    Tahar, S.2    Voicu, D.3    Song, X.4
  • 4
    • 0029699367 scopus 로고    scopus 로고
    • Integrating Formal Verification Methods with A Conventional Project Design Flow
    • A. Th. Eiriksson, "Integrating Formal Verification Methods with A Conventional Project Design Flow," in 33rd DAC, pp. 666-671, 1996.
    • (1996) 33rd DAC , pp. 666-671
    • Eiriksson, A.Th.1
  • 5
    • 0032288884 scopus 로고    scopus 로고
    • An Approach to Verify a Large Scale System-on-a-chip Using Symbolic Model Checking
    • K. Takayama, T. Satoh, T. Nakata, and F. Hirose, "An Approach to Verify a Large Scale System-on-a-chip Using Symbolic Model Checking," in ICCD, pp. 308-313, 1998.
    • (1998) ICCD , pp. 308-313
    • Takayama, K.1    Satoh, T.2    Nakata, T.3    Hirose, F.4
  • 6
    • 0033725172 scopus 로고    scopus 로고
    • Formal Verification of an Industrial System-on-a-chip
    • H. Choi, M.K. Yim, J.Y. Lee, B.W. Yun, and Y.T. Lee, "Formal Verification of an Industrial System-on-a-chip," in ICCD, 2000.
    • (2000) ICCD
    • Choi, H.1    Yim, M.K.2    Lee, J.Y.3    Yun, B.W.4    Lee, Y.T.5
  • 7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.