Verified optimizations for the intel* Ia-64 architecture**

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1869, Issue , 2000, Pages 215-232

  Grundy, Jim ^a  

^a AUSTRALIAN NATIONAL UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FORMAL LOGIC;

ASSEMBLY LEVELS; CODE OPTIMIZATION; FORMAL MODEL; THEOREM PROVERS;

THEOREM PROVING;

EID: 84949256764     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44659-1_14     Document Type: Conference Paper

References (10)

1. Jerry R. Burch and David L. Dill. Automatic verification of pipelined microprocessor control. In David L. Dill, editor, Computer Aided Verification: Proceedings of the 6th International Conference (CAV'94), volume 818 of Lecture Notes in Computer Science, pages 68-80, Stanford, California, June 1994. Springer-Verlag.
2. Michael Butler, Jim Grundy, Thomas Langbacka, Rimvydas Ruksenas, and Joakim von Wright. The refinement calculator: proof support for program refinement. In Lindsay Groves and Steve Reeves, editors, Formal Methods Pacific'97: Proceedings of FMP'97, Discrete Mathematics and Theoretical Computer Science, pages 40-61, Victoria University of Wellington, New Zealand, March 1997. Springer-Verlag.
3. Carole Dulong. The IA-64 architecture at work. Computer, 31(7):24-32, July 1998.
4. Mike Gordon. A formalization of a simplified subset of the Alpha shared memory model, http://www.cl.cam.ac.uk/Research/HVG/FTP/FTP.html#papers.
5. John Harrison. The HOL Light Manual. University of Cambridge, Computer Laboratory, New Museums Site, Pembroke Street, Cambridge CB2 3QG, England, edition 1.0, May 1998.
6. Intel. IA-64 application developer's architecture guide. Order number 245188, Intel Corporation, Santa Clara CA, USA, May 1999.
7. Robert Brent Jones. Applications of Symbolic Simulation to the Verification of Microprocessors. PhD thesis, Stanford University, Department of Electrical Engineering, 161 Packard, 350 Serra Mall, Stanford CA 94305, USA, August 1999.
8. Michael Norrish and Konrad Slind. The HOL System Description. University of Cambridge, Computer Laboratory, New Museums Site, Pembroke Street, Cambridge CB2 3QG, England, hol98 Taupo-2 edition, February 2000.
9. SPARC International. The SPARC Architecture Manual. Prentice-Hall, New Jersey, 8th edition, 1992.
10. 10. Joakim von Wright and Kaisa Sere. Program transformations and refinements in HOL. In Myla Archer, Jeffrey J. Joyce, Karl N. Levitt, and Phillip J. Windley, editors, The HOL Theorem Proving and its Applications: International Workshop, pages 231-239, University of California at Davis, August 1991. ACM-SIGDA, IEEE Computer Society Press.