메뉴 건너뛰기




Volumn 1346, Issue , 1997, Pages 54-56

Model checking

Author keywords

Automatic verification; Binary decision diagrams; Model checking; Temporal logic

Indexed keywords

BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; COMPUTER CIRCUITS; SPACE SHUTTLES; SPECIFICATIONS; TEMPORAL LOGIC;

EID: 84949215100     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0058022     Document Type: Conference Paper
Times cited : (140)

References (18)
  • 3
    • 8744222139 scopus 로고
    • Automatic circuit verification using temporal logic: Two new examples
    • Elsevier Science Publishers (North Holland)
    • M. C. Browne, E. M. Clarke, and D. Dill. Automatic circuit verification using temporal logic: Two new examples. In Formal Aspects of VLSI Design. Elsevier Science Publishers (North Holland), 1986.
    • (1986) Formal Aspects of VLSI Design
    • Browne, M.C.1    Clarke, E.M.2    Dill, D.3
  • 4
    • 0022890039 scopus 로고
    • Automatic verification of sequential circuits using temporal logic
    • C-35
    • M. C. Browne, E. M. Clarke, D. L. Dill, and B. Mishra. Automatic verification of sequential circuits using temporal logic. IEEE Transactions on Computers, C-35 (12):1035-1044, 1986.
    • (1986) IEEE Transactions on Computers , Issue.12 , pp. 1035-1044
    • Browne, M.C.1    Clarke, E.M.2    Dill, D.L.3    Mishra, B.4
  • 5
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • C-35
    • R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35 (8), 1986.
    • (1986) IEEE Transactions on Computers , Issue.8
    • Bryant, R.E.1
  • 6
    • 0003347456 scopus 로고
    • Symbolic model checking with partitioned transition relations
    • A. Halaas and P. B. Denyer, editors, August, Winner of the Sidney Michaelson Best Paper Award
    • J. R. Burch, E. M. Clarke, and D. E. Long. Symbolic model checking with partitioned transition relations. In A. Halaas and P. B. Denyer, editors, Proceedings of the 1991 International Conference on Very Large Scale Integration, August 1991. Winner of the Sidney Michaelson Best Paper Award.
    • (1991) Proceedings of the 1991 International Conference on Very Large Scale Integration
    • Burch, J.R.1    Clarke, E.M.2    Long, D.E.3
  • 10
    • 0002367651 scopus 로고
    • Synthesis of synchronization skeletons for branching time temporal logic
    • Yorktown Heights, NY, May, Lecture Notes in Computer Science. Springer-Verlag, 1981
    • E. M. Clarke and E. A. Emerson. Synthesis of synchronization skeletons for branching time temporal logic. In Logic of Programs: Workshop, Yorktown Heights, NY, May 1981, volume 131 of Lecture Notes in Computer Science. Springer-Verlag, 1981.
    • (1981) Logic of Programs: Workshop , vol.131
    • Clarke, E.M.1    Emerson, E.A.2
  • 11
  • 13
    • 0022776452 scopus 로고
    • Automatic verification of asynchronous circuits using temporal logic
    • Part E
    • D. L. Dill and E. M. Clarke. Automatic verification of asynchronous circuits using temporal logic. IEE Proceedings, Part E 133(5), 1986.
    • (1986) IEE Proceedings , vol.133 , Issue.5
    • Dill, D.L.1    Clarke, E.M.2
  • 14
    • 0025212803 scopus 로고
    • Software for analytical development of communications protocols
    • Jan.-Feb
    • Z. Har’El and R. P. Kurshan. Software for analytical development of communications protocols. AT&T Technical Journal, 69(1):45-59, Jan.-Feb. 1990.
    • (1990) AT&T Technical Journal , vol.69 , Issue.1 , pp. 45-59
    • Har’El, Z.1    Kurshan, R.P.2
  • 16
    • 0021899094 scopus 로고
    • Hierarchical verification of asynchronous circuits using temporal logic
    • B. Mishra and E.M. Clarke. Hierarchical verification of asynchronous circuits using temporal logic. Theoretical Computer Science, 38:269-291, 1985.
    • (1985) Theoretical Computer Science , vol.38 , pp. 269-291
    • Mishra, B.1    Clarke, E.M.2
  • 17
    • 0038030702 scopus 로고
    • A computational theory and implementation of sequential hardware equivalence
    • R. Kurshan and E. Clarke, editors, also DIMACS Tech. Report 90-31, Rutgers University, NJ, June
    • C. Pixley. A computational theory and implementation of sequential hardware equivalence. In R. Kurshan and E. Clarke, editors, Proc. CAV Workshop (also DIMACS Tech. Report 90-31), Rutgers University, NJ, June 1990.
    • (1990) Proc. CAV Workshop
    • Pixley, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.