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Volumn 2002-January, Issue , 2002, Pages 202-205

Performance evaluation of JPEG-2000 on VLIW microarchitectures

Author keywords

Arithmetic; Image coding; ISO standards; Microarchitecture; Processor scheduling; Satellites; Streaming media; Transform coding; VLIW; Wavelet transforms

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; DIGITAL IMAGE STORAGE; IMAGE CODING; IMAGE PROCESSING; MEDIA STREAMING; MICROELECTRONICS; PROGRAM COMPILERS; SATELLITES; WAVELET TRANSFORMS;

EID: 84948984932     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM-02.2002.1161530     Document Type: Conference Paper
Times cited : (5)

References (13)
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    • V.1.500.4, ISO/IEC JTC1/SC29/WG1 (ITU-T SG8) N2415, Dec
    • M.D.Adams, "Jasper Software Reference Manual", V.1.500.4, ISO/IEC JTC1/SC29/WG1 (ITU-T SG8) N2415, Dec. 2001.
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    • Adams, M.D.1
  • 4
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    • Multimedia Processor-Based Implementation of an Error Diffusion Halftoning Algorithm Exploiting Subword Parallelism
    • Feb
    • J.Ahn and W.sung, "Multimedia Processor-Based Implementation of an Error Diffusion Halftoning Algorithm Exploiting Subword Parallelism", pp.129-138, IEEE Trans. on Circuits and Systems for Video Technology, Vol.11, No.2, Feb. 2001.
    • (2001) IEEE Trans. on Circuits and Systems for Video Technology , vol.11 , Issue.2 , pp. 129-138
    • Ahn, J.1    Sung, W.2
  • 5
    • 0035505586 scopus 로고    scopus 로고
    • An 80/20-Mhz 160-mW Multimedia Processor Integrated With Embedded DRAM, MPEG-4 Accelerator, and 3D Rendering Engine for Mobile Applications
    • Nov
    • C.Yoon, R.Woo, J.Kook and al., " An 80/20-Mhz 160-mW Multimedia Processor Integrated With Embedded DRAM, MPEG-4 Accelerator, and 3D Rendering Engine for Mobile Applications", pp.1758-1767, Vol.36, No.11, IEEE Journal of Solid-State Circuits, Nov.2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.11 , pp. 1758-1767
    • Yoon, C.1    Woo, R.2    Kook, J.3
  • 6
    • 0035506737 scopus 로고    scopus 로고
    • A 250-Mhz Single-Chip Multiprocessor for Audio and Video Signal Processing
    • Nov
    • T.Koyama, K.Inoue, H.Hanaki, M.Yasue and E.Iwata, "A 250-Mhz Single-Chip Multiprocessor for Audio and Video Signal Processing", pp. 1768-1774, Vol.36, No.11, IEEE Journal of Solid-State Circuits, Nov.2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.11 , pp. 1768-1774
    • Koyama, T.1    Inoue, K.2    Hanaki, H.3    Yasue, M.4    Iwata, E.5
  • 7
    • 0036110783 scopus 로고    scopus 로고
    • An 8-way VLIW Embedded Multimedia Processor Built in a 7-layer Metal 0.11 ?m CMOS Technology
    • San Francisco, Feb
    • H.Okano and al.,"An 8-way VLIW Embedded Multimedia Processor Built in a 7-layer Metal 0.11 ?m CMOS Technology", IEEE International Solid-state Circuits Conference, San Francisco, Feb.2002.
    • (2002) IEEE International Solid-state Circuits Conference
    • Okano, H.1
  • 12
    • 0034226001 scopus 로고    scopus 로고
    • SPEC CPU 2000: Measuring CPU Performance in the New Millennium
    • July
    • J.L.Henning, "SPEC CPU 2000: Measuring CPU Performance in the New Millennium", IEEE Computer, pp.28-25, July 2000.
    • (2000) IEEE Computer , pp. 28-125
    • Henning, J.L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.