Two-stage parallel partial retraining scheme for defective multi-layer neural networks

Proceedings - 4th International Conference/Exhibition on High Performance Computing in the Asia-Pacific Region, HPC-Asia 2000

Volumn 2, Issue , 2000, Pages 642-647

  Yamamori, K ^a   Abe, T ^a   Horiguchi, S ^a  

^a JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION ALGORITHMS; DEFECTS; NEURAL NETWORKS; RECONFIGURABLE HARDWARE;

BP ALGORITHM; CHIP AREAS; DEFECT COMPENSATION; HARDWARE DEVICES; HIGH SPEED; LEARNING CIRCUIT;

NETWORK LAYERS;

EID: 84948760985     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPC.2000.843515     Document Type: Conference Paper

References (8)

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