Hierarchical verification using verification diagrams

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1179, Issue , 1996, Pages 277-286

  Browne, I A ^a   Manna, Z ^a   Sipma, H B ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84947903165     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0027800     Document Type: Conference Paper

References (9)

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3. A. Browne, Z. Manna, and H.B. Sipma. Generalized verification diagrams.. In 15th Conference on the Foundations of Software Technology and Theoretical Computer Science, volume 1026 of LNCS, pages 484-498, December 1995.
4. L. de Alfaro and Z. Manna. Temporal verification by diagram transformations. In Proc. 8th Intl. Conference on Computer Aided Verification, July 1996.
5. D. Harel. Statecharts: A visual formalism for complex systems. Set. Comp. Prog., 8:231-274, 1987.
6. Z. Manna and A. Pnueli. Temporal verification diagrams. In Proc. Int. Symp. on Theoretical Aspects of Computer Software, volume 789 of LNCS, pages 726-765. Springer-Verlag, 1994.
7. Z. Manna and A. Pnueli. Temporal Verification of Reactive Systems: Safety. Springer-Verlag, New York, 1995.
8. Z Manna and P. Wolper. Synthesis of communicating processes from temporal logic specifications. ACM Trans. Prog. Lang. Sys., 6(l):68-93, January 1984.
9. P. Wolper. Temporal logic can be more expressive. Information and Control, 56:72-99, 1983.