Exploring optimal cost-performance designs for Raw microprocessors

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 1-16

  Moritz, Csaba Andras ^a   Yeung, Donald ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; COSTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRAIN SIZE AND SHAPE; INTEGRATED CIRCUIT INTERCONNECTS; MEMORY ARCHITECTURE; SEMICONDUCTOR DEVICE MANUFACTURE; VLSI CIRCUITS;

ARCHITECTURAL MODELING; HARDWARE STRUCTURES; INSTRUCTION LEVEL PARALLELISM; PROCESSING ELEMENTS; PROCESSING POWER; PROPOSED ARCHITECTURES; SEMICONDUCTOR INDUSTRY; TOTAL CHIP AREA;

COST BENEFIT ANALYSIS;

EID: 84947594065     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707877     Document Type: Conference Paper

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