A self-reconfigurable gate array architecture

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 106-120

  Sidhu, Reetinder ^a   Wadhwa, Sameer ^a   Mei, Alessandro ^b   Prasanna, Viktor K ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b UNIVERSITY OF TRENTO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTATION THEORY; DATA TRANSFER; FORESTRY; LOGIC DEVICES; MEMORY ARCHITECTURE; MESH GENERATION; RANDOM ACCESS STORAGE; RECONFIGURABLE ARCHITECTURES; SWITCHING; TOPOLOGY;

CONTEXT SWITCH; CONTEXT SWITCHING; MEMORY LOCATIONS; MESH OF TREES; PHYSICAL PROXIMITY; RECONFIGURABLE DEVICES; SELF RECONFIGURATION; SELF-RECONFIGURABLE;

RECONFIGURABLE HARDWARE;

EID: 84947593210     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_12     Document Type: Conference Paper

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