-
1
-
-
0003849991
-
-
PhD Thesis, AI Technical Report 1586, MIT, 545 Technology Sq., Cambridge, MA02139, Sept.
-
A. DeHon, Reconfigurable Architectures for General Purpose Computing, PhD Thesis, AI Technical Report 1586, MIT, 545 Technology Sq., Cambridge, MA02139, Sept. 1996, http://www. ai. mit. edu/people/andre/phd. html.
-
(1996)
Reconfigurable Architectures for General Purpose Computing
-
-
DeHon, A.1
-
2
-
-
84947282132
-
-
Xilinx Corp., Virtex-II 1. 5V, Field-Programmable Gate Arrays (v1. 7)-Advance Product Specification, October 2
-
Xilinx Corp., Virtex-II 1. 5V, Field-Programmable Gate Arrays (v1. 7)-Advance Product Specification, October 2, 2001, http://www. xilinx. com.
-
(2001)
-
-
-
3
-
-
84893562557
-
A run-time reconfigurable engine for image interpolation
-
Napa Valley, CA, USA, April 15-17
-
R. D. Hudson, D. I. Lehn, and P. M. Athanas, "A Run-Time Reconfigurable Engine for Image Interpolation, " in Proc. of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, USA, April 15-17, 1998.
-
(1998)
Proc. of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines
-
-
Hudson, R.D.1
Lehn, D.I.2
Athanas, P.M.3
-
4
-
-
84893641728
-
A decade of reconfigurable computing: A visionary retrospective
-
Munich, Germany, March 12-15
-
R. Hartenstein, "A Decade of Reconfigurable Computing: A Visionary Retrospective, " In Int'l Conf. on Design, Automation and Test in Europe (DATE'01), Munich, Germany, March 12-15, 2001, pp. 642-649.
-
(2001)
Int'l Conf. on Design, Automation and Test in Europe (DATE'01)
, pp. 642-649
-
-
Hartenstein, R.1
-
5
-
-
79955142752
-
XPP-VC: A c compiler with temporal partitioning for the pact-xpp architecture
-
Montpellier, France, Sept. 2-4, LNCS, Springer-Verlag
-
J. M. P. Cardoso, and M. Weinhardt, "XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture, " in Proc. of the 12th Int'l Conference on Field Programmable Logic and Applications (FPL'02), Montpellier, France, Sept. 2-4, 2002, LNCS, vol. 2438, Springer-Verlag, pp. 864-874.
-
(2002)
Proc. of the 12th Int'l Conference on Field Programmable Logic and Applications (FPL'02)
, vol.2438
, pp. 864-874
-
-
Cardoso, J.M.P.1
Weinhardt, M.2
-
6
-
-
0032681537
-
An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of dsp applications
-
New Orleans, LA, USA, June 21-25
-
M. Kaul, R. Vemuri, S. Govindarajan, and I. E. Ouaiss, "An Automated Temporal Partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications, " in Proc. of the IEEE/ACM Design Automation Conference (DAC'99), New Orleans, LA, USA, June 21-25, 1999, pp. 616-622.
-
(1999)
Proc. of the IEEE/ACM Design Automation Conference (DAC'99)
, pp. 616-622
-
-
Kaul, M.1
Vemuri, R.2
Govindarajan, S.3
Ouaiss, I.E.4
-
7
-
-
84950126740
-
Fast and guaranteed c compilation onto the pact-xpp reconfigurable computing platform
-
IEEE Computer Society Press, Los Alamitos, CA, USA
-
J. M. P. Cardoso, and M. Weinhardt, "Fast and Guaranteed C Compilation onto the PACT-XPP Reconfigurable Computing Platform, " In Proc. of the IEEE 10th Symposium on Field-Programmable Custom Computing Machines (FCCM'02), IEEE Computer Society Press, Los Alamitos, CA, USA, 2002, pp. 291-292.
-
(2002)
Proc. of the IEEE 10th Symposium on Field-Programmable Custom Computing Machines (FCCM'02)
, pp. 291-292
-
-
Cardoso, J.M.P.1
Weinhardt, M.2
-
8
-
-
33646898651
-
-
PACT XPP Technologies, Inc. Release 2. 1. 1 March
-
PACT XPP Technologies, Inc., "The XPP White Paper, " Release 2. 1. 1, March 2002, http://www. pactxpp. com.
-
(2002)
The XPP White Paper
-
-
-
9
-
-
84893733998
-
From c programs to the configure-execute model
-
Munich, Germany, March 3-7, IEEE Computer Society Press, (to appear
-
J. M. P. Cardoso, and M. Weinhardt, "From C Programs to the Configure-Execute Model, " in Proc. of the Design, Automation and Test in Europe Conference (DATE'03), Munich, Germany, March 3-7, 2003, IEEE Computer Society Press, (to appear).
-
(2003)
Proc. of the Design, Automation and Test in Europe Conference (DATE'03)
-
-
Cardoso, J.M.P.1
Weinhardt, M.2
-
10
-
-
0028743437
-
Compiler transformations for high-performance computing
-
December
-
D. F. Bacon, S. L. Graham, and O. J. Sharp, "Compiler Transformations for High-Performance Computing, " In ACM Computing Surveys, Vol. 26, No. 4, December 1994, pp. 345-420.
-
(1994)
ACM Computing Surveys
, vol.26
, Issue.4
, pp. 345-420
-
-
Bacon, D.F.1
Graham, S.L.2
Sharp, O.J.3
-
11
-
-
0003502903
-
-
Morgan Kaufmann Publishers, Inc., San Francisco, CA, USA
-
S. S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, Inc., San Francisco, CA, USA, 1997.
-
(1997)
Advanced Compiler Design and Implementation
-
-
Muchnick, S.S.1
-
12
-
-
0347009867
-
-
PhD Thesis, Univ. of Illinois at Urbana-Champaign, Dept. of Computer Science, Report, 71-424 Feb.
-
Y. Muraoka, Parallelism exposure and exploitation in programs, PhD Thesis, Univ. of Illinois at Urbana-Champaign, Dept. of Computer Science, Report, 71-424, Feb. 1971.
-
(1971)
Parallelism Exposure and Exploitation in Programs
-
-
Muraoka, Y.1
-
13
-
-
0017465222
-
A survey of parallel machine organization and programming
-
January, ACM Press, New York, USA
-
David J. Kuck, "A survey of parallel machine organization and programming, " in ACM Computing Surveys (CSUR), Vol. 9, Issue 1, January 1977, ACM Press, New York, USA, pp. 29-59.
-
(1977)
ACM Computing Surveys (CSUR)
, vol.9
, Issue.1
, pp. 29-59
-
-
Kuck, D.J.1
-
14
-
-
84976692695
-
SUIF: An infrastructure for research on parallelizing and optimizing compilers
-
Dec.
-
R. Wilson, et al., "SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers, " In ACM SIGPLAN Notices, Vol. 29, No. 12, Dec. 1996. http://suif. stanford. edu.
-
(1996)
ACM SIGPLAN Notices
, vol.29
, Issue.12
-
-
Wilson, R.1
-
15
-
-
0035248229
-
Pipeline vectorization
-
Feb.
-
M. Weinhardt, and W. Luk, "Pipeline Vectorization, " In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2. Feb. 2001, pp. 234-233.
-
(2001)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.2
, pp. 234-233
-
-
Weinhardt, M.1
Luk, W.2
-
16
-
-
0142130823
-
An integrated temporal partitioning and partial reconfiguration technique for design latency improvement
-
Paris, France, March 27-30
-
S. Ganesan, and R. Vemuri, "An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement, " in Proc. of Design, Automation & Test in Europe (DATE'00), Paris, France, March 27-30, 2000, pp. 320-325.
-
(2000)
Proc. of Design, Automation & Test in Europe (DATE'00)
, pp. 320-325
-
-
Ganesan, S.1
Vemuri, R.2
-
17
-
-
84947576966
-
Dataflow partitioning and scheduling algorithms for wasmii, a virtual hardware
-
Villach, Austria, August 27-30, LNCS, Springer-Verlag, Berlin
-
A. Takayama, Y. Shibata, K. Iwai, and H. Amano, "Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware, " in Proc. of the 10th Int'l Conference on Field-Programmable Logic and Applications (FPL'00), Villach, Austria, August 27-30, 2000, LNCS, vol. 1896, Springer-Verlag, Berlin, pp. 685-694.
-
(2000)
Proc. of the 10th Int'l Conference on Field-Programmable Logic and Applications (FPL'00)
, vol.1896
, pp. 685-694
-
-
Takayama, A.1
Shibata, Y.2
Iwai, K.3
Amano, H.4
-
18
-
-
0034174187
-
Piperench: A reconfigurable architecture and compiler
-
April
-
S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor, "PipeRench: A Reconfigurable Architecture and Compiler, " In IEEE Computer, Vol. 33, No. 4, April 2000, pp. 70-77.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 70-77
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.R.6
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