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Volumn 2144, Issue , 2001, Pages 126-139

Register transformations with multiple clock domains

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC;

EID: 84947276260     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44798-9_11     Document Type: Conference Paper
Times cited : (1)

References (18)
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    • Cabodi, G.1    Quer, S.2    Somenzi, F.3
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    • Simulation strategy after model checking, Validation, and Test Workshop, IEEE
    • Hoon Choi, Byeong-WheeYun andYun-Tae Lee. Simulation strategy after model checking: Experience in industrial SOC design. In International High-Level Design, Validation, and Test Workshop, pages 77–79. IEEE, 2000.
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    • 84893570873 scopus 로고    scopus 로고
    • Retiming sequential circuits with multiple register classes
    • IEEE, March
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    • ACM/IEEE
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    • Hassoun, S.1    Ebeling, C.2
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    • 0030704430 scopus 로고    scopus 로고
    • Optimizing twophase, level-clocked circuitry
    • January, An earlier version of this paper appear in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, March 1992
    • Alexander T. Ishii, Charles E. Leiserson, and Marios C. Papaefthymiou. Optimizing twophase, level-clocked circuitry. Journal of the ACM, 44(1):148–199, January 1997. An earlier version of this paper appear in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, March 1992.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.