The design and verification of a sorter core

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2144, Issue , 2001, Pages 355-368

  Claessen, Koen ^a   Sheeran, Mary ^a   Singh, Satnam ^b  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FORMAL LOGIC;

CONNECTION PATTERNS; DESIGN STYLES; GENERIC CIRCUITS; MERGING NETWORKS; SORTING NETWORK;

INTEGRATED CIRCUIT DESIGN;

EID: 84947206106     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44798-9_28     Document Type: Conference Paper

References (10)

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