A radiation-hard phase-locked loop

IEEE International Symposium on Industrial Electronics

Volumn II, Issue , 2003, Pages 901-906

  Pan, Dong ^a   Li, H W ^a   Wilamowski, B M ^a  

^a UNIVERSITY OF IDAHO   (United States)

Author keywords

Circuit simulation; Clocks; Degradation; Frequency; Phase locked loops; Radiation effects; Radiation hardening; Signal generators; Signal processing; Temperature

Indexed keywords

CIRCUIT SIMULATION; CLOCKS; DEGRADATION; DELAY CIRCUITS; ELECTRIC CLOCKS; HARDENING; INDUSTRIAL ELECTRONICS; JITTER; LOCKS (FASTENERS); PHASE LOCKED LOOPS; RADIATION; RADIATION HARDENING; SIGNAL GENERATORS; SIGNAL PROCESSING; TEMPERATURE;

FREQUENCY; FREQUENCY MULTIPLIER; HIGH FREQUENCY CLOCKS; PEAK-TO-PEAK JITTER; PHASELOCKED LOOP (PLLS); POST LAYOUT SIMULATION; PROCESS ,TEMPERATURE AND VOLTAGES; PROGRAMMABLE CLOCKS;

RADIATION EFFECTS;

EID: 84946140281     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISIE.2003.1267941     Document Type: Conference Paper

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