Validating real-time constraints in embedded systems

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC

Volumn 2001-January, Issue , 2001, Pages 347-355

  Shyamasundar, R K ^a   Aghav, J V ^a  

^a TATA INSTITUTE OF FUNDAMENTAL RESEARCH   (India)

Author keywords

Embedded systems; Esterel; Real time systems; Synchronous languages; Validation verification

Indexed keywords

APPLICATION PROGRAMS; COMPUTATIONAL LINGUISTICS; CONCRETES; EMBEDDED SYSTEMS; ESTERS; HARDWARE-SOFTWARE CODESIGN; INTERACTIVE COMPUTER SYSTEMS; SPECIFICATIONS;

CONCRETE ARCHITECTURE; EMBEDDED REAL TIME SYSTEMS; ESTEREL; LOGICAL SPECIFICATIONS; PROGRAMMING ENVIRONMENT; REAL TIME CONSTRAINTS; SYNCHRONOUS LANGUAGES; TIMING CONSTRAINTS;

REAL TIME SYSTEMS;

EID: 84945932311     PISSN: 15410110     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2001.992719     Document Type: Conference Paper

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