Characteristics and Three-Dimensional Integration of MOSFET’s in Small-Grain LPCVD Polycrystalline Silicon

IEEE Transactions on Electron Devices

Volumn 32, Issue 2, 1985, Pages 258-281

  Malhi, Satwinder D S ^a   Shichijo, Hisashi ^a   Sanjay, S K ^a   Banerjee, B ^a   Sundaresan, Ravishankar ^a   Elahy, Mostafa ^a   Pollack, Gordon P ^a   Richardson, William F ^a   Shah, Ashwin H ^a   Hite, Larry R ^a   Womack, Richard H ^a   Chatterjee, Pallab K ^a   Lam, Hon Wai ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84945714601     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1985.21939     Document Type: Article

References (68)

1. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, 1974.
2. H. Shichijo, “A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI,” in IEDM Tech. Dig., pp. 219–222, 1981.
3. K. Itoh, R. Hori, J. Etoh, S. Asai, N. Hashimoto, K. Yagi, and H. Sunami, “An experimental 1Mb DRAM with on-chip voltage limiter,” in ISSCC Tech. Dig., pp. 282–283, 1984.
4. J. F. Gibbons and K. F. Lee, “One-gate-wide CMOS inverter on laser-recrystallized polysilicon,” IEEE Electron Device Lett., vol. EDL-1, pp. 117–118, 1980.
5. J. E. A. Maurits, “SOS wafers—Some comparisons to silicon wafers,” IEEE Trans. Electron Devices, vol. ED-25, pp. 859–863, 1978.
6. A. F. Tasch Jr., T. C. Holloway, K. F. Lee, and J. F. Gibbons, “Silicon-on-insulator MOSFET’s fabricated on laser-annealed polysilicon on SiO2,” Electron. Lett., vol. 15, pp. 435–437, 1979.
7. J. Y. Chen and D. B. Rensch, “N-channel MOSFET’s fabricated in silicon-on-oxide using a scanning e-beam line source,” in DRC Tech. Dig., paper VB-6, 1983.
8. T. J. Stultz and J. F. Gibbons, “Arc lamp zone melting and recrystallization of silicon films on oxidized silicon substrates,” Appl. Phys. Lett., vol. 41, pp. 824–826, 1982.
9. S. Sugiura, T. Yoshida, Y. Kaneko, K. Shono, and D. J. Dumin, “MOS transistors fabricated on multiple silicon-insulator layers,” in DRC Tech. Dig., paper VB-7, 1984.
10. K. Izumi, M. Doken, and H. Ariyoshi, “CMOS devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon,” Electron. Lett., vol. 14, pp. 593–595, 1978.
11. J. C. C. Fan, M. W. Geis, and B.-Y. Tsaur, “Lateral epitaxy by seeded solidification for growth of single-crystal Si films on insulators,” Appl. Phys. Lett., vol. 38, pp. 365-367,1981.
12. S. D. S. Malhi, R. R. Shah, P. K. Chatterjee, H. W. Lam, R. F. Pinizzotto, C. E. Chen, H. Shichijo, and D. W. Bellavance, “Characteristics of p-channel MOSFET’s in LPCVD polysilicon and effect of grain boundary passivation on device performance,” in DRC Tech. Dig., paper VB-1, 1983.
13. C. H. Fa and T. T. Jew, “The polysilicon insulated gate field effect transistor,” IEEE Trans. Electron Devices, vol. ED-13, pp. 290–291, 1966.
14. T. I. Kamins, “Field-effects in polycrystalline-silicon films,” Solid-State Electron., vol. 15, pp. 789–799, 1972.
15. T. Iizuka, H. Nozawa, Y. Mizutani, H. Kaneko, and S. Kohyama, “Variable resistance polysilicon for high density CMOS RAM,” in IEDM Tech. Dig., pp. 370–374, 1979.
16. T. I. Kamins and P. J. Marcoux, “Hydrogenation of transistors fabricated in polycrystalline-silicon films,” IEEE Electron Device Lett., vol. EDL-1, pp. 159–161, 1980.
17. S. W. Depp, A. Juliana, and B. G. Huth, “Polysilicon FET devices for large area input/output applications,” in IEDM Tech. Dig., pp. 703–707, 1980.
18. S. Onga, Y. Mizutani, K. Taniguchi, M. Kashiwagi, K. Shibata, and S. Kohyama, “Characterization of polycrystalline silicon MOS transistors and its film properties—I,” Japan. J. Appl. Phys., vol. 21, pp. 1472–1478, 1982.
19. Y. Hirai, Y. Osada, T. Komatsu, S. Omata, K. Aihara, and T. Nakagiri, “Glow discharge polycrystalline silicon thin film transistors,” Appl. Phys. Lett., vol. 42, pp. 701–703, 1983.
20. S. D. S. Malhi, P.K. Chatterjee, R. F. Pinizzotto, H. W. Lam, C. E. Chen, H. Shichijo, R. R. Shah, and D. W. Bellavance, “p-channel MOSFET’s in LPCVD polysilicon,” IEEE Electron Device Lett., vol. EDL-4, pp. 369–371, 1983.
21. S. Morozumi, K. Oguchi, S. Yazawa, T. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video displays addressed by poly Si TFT’s,” in SID 83 Dig., pp. 156–157, 1983.
22. L. L. Kazmerski, Polysilicon and Amorphous Thin Film Devices. New York: Academic, 1980.
23. G. Yaron and D. Frohman-Bentchkowsky, “Capacitance-voltage characterization of poly Si-SiO2-Si structures,” Solid-State Electron., vol. 23, pp. 433–439, 1980.
24. S. D. S. Malhi, R. R. Shah, H. Shichijo, R. F. Pinizzotto, C. E. Chen, P. K. Chatterjee, and H. W. Lam, “Effects of grain boundary passivation on the characteristics of p-channel MOSFET’s in LPCVD polysilicon,” Electron. Lett., vol. 19, pp. 993–994, 1983.
25. H. R. Grinolds, S. S. Wong, T. W. Ekstedt, C. G. Sodini, S. H. Kwan, K. H. Jackson, and L. Martinez, “Nitrided-oxides for thin gate dielectrics in MOS devices,” in IEDM Tech. Dig., pp. 42–45, 1982.
26. M. Taguchi, S. Audo, S. Hijiya, T. Nakamura, S. Economo, and T. Yabu, “A capacitance coupled bit-line cell for Mb level DRAM’s,” in ISSCC Tech. Dig., pp. 100–101, 1984.
27. J. P. Colinge, E. Demoulin, and H. Morel, “Field-effect in large grain polysilicon transistors,” in IEDM Tech. Dig., pp. 444–447, 1982.
28. J. P. Colinge, H. Morel, and J. P. Chante, “Field effect in large grain polycrystalline silicon,” IEEE Trans. Electron Devices, vol. ED-30, pp. 197–201, 1983.
29. E. A. Grey and G. T. Higgins, “Solute limited grain boundary migration,” ACTA Met., vol. 21, pp. 309–321, 1973.
30. Y. Ohmura, K. Shibata, T. Inoue, T. Yoshii, and Y. Horiike, “Characteristics of MOS devices in electron beam-recrystallized silicon on insulator,” in IEDM Tech. Dig., pp. 429–432, 1982.
31. M. W. Geis, H. I. Smith, C. K. Chen, B-Y. Tsaur, R. W. Mountain, and D. J. Silversmith, “Subboundary entrainment in strip-heater-recrystallized Si films,” in Abst. MRS Spring Meeting, paper D2.2, 1984.
32. C. H. Seager and D. S. Ginley, “Studies of the hydrogen passivation of silicon grain boundaries,” J. Appl. Phys., vol. 52, pp. 1050–1055, 1981.
33. G. P. Pollack, W. F. Richardson, S. D. S. Malhi, T. Bonifield, H. Shichijo, S. Banerjee, M. Elahy, A. H. Shah, R. Womack, and P. K. Chatterjee, “Hydrogen passivation of polysilicon MOSFET’s from a plasma nitride source,” IEEE Electron Device Lett., vol. EDL-5, pp. 468–470, 1984.
34. W. A. Lanford and M. J. Rand, “The hydrogen content of plasma deposited silicon nitride,” J. Appl. Phys., vol. 49, pp. 2473–2477, 1978.
35. H. J. Singh, K. C. Saraswat, J. D. Shott, J. P. McVittie, and J. D. Meindl, “Scaling of SOI/PMOS transistors,” in IEDM Tech. Dig., pp. 67–69, 1983.
36. J. Y. W. Seto, “Electrical properties of polycrystalline silicon films,” J. Appl. Phys., vol. 46, pp. 5247–5254, 1975.
37. S. K. Banerjee, M. Elahy, H. Shichijo, G. P. Pollack, W. F. Richardson, S. D. S. Malhi, A. H. Shah, P. K. Chatterjee, H. W. Lam, and R. H. Womack, “Comparison of accumulation and inversion mode LPCVD polysilicon MOSFET characteristics for memory applications,” in DRC Tech. Dig., paper VB-5, 1984.
38. M. M. Mandurah, K. C. Saraswat, C. R. Helms, and T. I. Kamins, “Doping segregation in polycrystalline silicon,” J. Appl. Phys., vol. 51, pp. 5755–5760, 1980.
39. H. C. de Graaff and J. G. de Groot, “Polysilicon devices in bipolar IC technology,” in IEDM Tech. Dig., pp. 46–49, 1980.
40. N.C-C. Lu, L. Gerzberg, C.-Y. Lu, and J. D. Meindl, “Modeling and optimization of monolithic polycrystalline silicon resistors,” IEEE Trans. Electron Devices, vol. ED-28, pp. 818–830, 1981.
41. D. M. Kim, A. N. Khondker, S. S. Ahmed, and R. R. Shah, “Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system—Part I: Small signal theory,” IEEE Trans. Electron Devices, vol. ED-31, pp. 480–493, 1984.
42. J. G. Fossum and A. Ortiz-Conde, “Effects of grain boundaries on the channel conductance of SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, pp. 933–940, 1983.
43. K. K. Ng, G. K. Celler, E. I. Povilonis, R. C. Frye, H. J. Leamy, and S. M. Sze, “Effects of grain boundaries on laser crystallized poly-Si MOSFET’s,” IEEE Electron Device Lett., vol. EDL-2, pp. 316–318, 1981.
44. E. A. Irene, E. Tierney, and D. W. Dong, “Silicon oxidation studies: Morphological aspects of the oxidation of polycrystalline silicon,” J. Electrochem. Soc., vol. 127, pp. 705–713, 1980.
45. G. Harbeke, L. Krausbauer, E. F. Steigmeier, A. E. Widmer, H. F. Kappert, and G. Neugebauer, “High quality polysilicon by amorphous low pressure chemical vapor deposition,” Appl. Phys. Lett., vol. 42, pp. 249–251, 1983.
46. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n-p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, pp. 871–876, 1983.
47. A. N. Khondker, S. S. Ahmed, T. Liou, and D. M. Kim, “Modeling of polysilicon resistors, p-n junction diodes and MOSFET’s,” in Abst. MRS Spring Meeting, paper D4.6, 1984.
48. J. Tihanyi and H. Schlotterer, “Influence of floating substrate potential on the characteristics of ESFI MOS transistors,” Solid-State Electron., vol. 18, pp. 309–314, 1975.
49. H. K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1244–1251, 1983.
50. P. Yang and P. K. Chatterjee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Trans. Computer-Aided Design of ICAS, vol. CAD-1, pp. 169–182, 1982.
51. A. Ortiz-Conde and J. G. Fossum, “Moderate inversion in SOI MOSFET’s with grain boundaries,” IEEE Electron Device Lett., vol. EDL-4, pp. 344–346, 1983.
52. T. Ohzone, T. Hirao, K. Tsuji, S. Horiuchi, and S. Takayangi, “2K×8 bit static RAM,” in IEDM Tech. Dig., pp. 360–363, 1978.
53. K. L. Wang, A. H. Shah, H. Shichijo, C. D. Gosmeyer, and P. K. Chatterjee, “A subthreshold load element for high density static RAM,” in IEDM Tech. Dig., pp. 628–631, 1982.
54. J. P. Colinge and E. Demoulin, “ST-CMOS (stacked transistors CMOS): A double-poly-NMOS-compatible CMOS technology,” in IEDM Tech. Dig., pp. 557–560, 1981.
55. G. T. Goeloe, E. W. Maby, D. J. Silversmith, R. W. Mountain, and D. A. Antoniadis, “Vertical single-gate CMOS inverters on laser-processed multilayer substrates,” in IEDM Tech. Dig., pp. 554–556, 1981.
56. J. P. Colinge, E. Demoulin, and M. Lobet, “Stacked transistors CMOS (ST-CMOS), an NMOS technology modified to CMOS,” IEEE Trans. Electron Devices, vol. ED-29, pp. 585–589, 1982.
57. C. E. Chen, H. W. Lam, S. D. S. Malhi, and R. F. Pinizzotto, “Stacked CMOS SRAM cell,” IEEE Electron Device Lett., vol. EDL-4, pp. 272–274, 1983.
58. S. D. S. Malhi, R. Karnaugh, A. H. Shah, L. Hite, P. K. Chatterjee, H. E. Davis, S. S. Mahant-Shetti, C. D. Gosmeyer, R. S. Sundaresan, C. E. Chen, H. W. Lam, R. A. Haken, R. F. Pinizzotto, and R. K. Hester, “A VLSI suitable 2 μm stacked CMOS process,” in DRC Tech. Dig., paper VB-1, 1984.
59. S. D. S. Malhi, P. K. Chatterjee, T. D. Bonifield, J. E. Leiss, D. E. Carter, R. F. Pinizzotto, and D. J. Coleman, “Edge defined self-alignment of submicrometer overlaid devices,” IEEE Electron Device Lett., vol. EDL-5, 1984.
60. M. Elahy, unpublished.
61. R. Sundaresan, S. D. S. Malhi, L. R. Hite, A. H. Shah, H. W. Lam, and P. K. Chatterjee, “A fully self-aligned stacked CMOS 64K SRAM,” in IEDM Tech. Dig., pp. 871–873, 1984.
62. A. H. Shah, L. R. Hite, S. S. Mahant-Shetti, P. K. Chatterjee, H. E. Davis, R. K. Hester, S. D. S. Malhi, R. Karnaugh, C. D. Gosmeyer, R. Sundaresan, C. E. Chen, H. W. Lam, and R. A. Haken, “A 2 μm Stacked CMOS 64K SRAM,” in VLSI Symp. Tech. Dig., 1984.
63. R. D. Jolly, T. I. Kamins, and R. H. McCharles, “A dynamic RAM cell in recrystallized polysilicon,” IEEE Electron Device Lett., vol. EDL-4, pp. 8–11, 1983.
64. J. C. Sturm, M. D. Giles, and J. F. Gibbons, “A three-dimensional folded dynamic RAM in beam-recrystallized polysilicon,” IEEE Electron Device Lett., vol. EDL-5, 151–153, 1984.
65. T. C. May and M. H. Wood, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Trans. Electron Devices, vol. ED-26, pp. 2–9, 1979.
66. H. Shichijo, S. D. S. Malhi, A. H. Shah, G. P. Pollack, W. F. Richardson, M. Elahy, S. Banerjee, R. Womack, and P. K. Chatterjee, “TITE RAM: A new SOI DRAM cell for Mbit DRAM’s,” in Extended Abst. 1984 Int. Conf. Solid State Devices and Materials (Kobe, Japan), 265–268, 1984.
67. H. Shichijo, S. D. S. Malhi, P. K. Chatterjee, R. R. Shah, M. A. Douglas, and H. W. Lam, “Characterization of n-channel and p-channel LPCVD polysilicon MOSFET’s,” in IEDM Tech. Dig., pp. 202–205, 1983.
68. J. E. Leiss, P. K. Chatterjee, and T. C. Holloway, “DRAM design using the taper-isolated dynamic RAM cell,” IEEE Trans. Electron Devices, vol. ED-29, pp. 707–713, 1982.