A VLSI design of hierarchical search motion estimation processor chip

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 247-249

  Seo, Young San ^a   You, Jae Hee ^a  

^a Hong Ik University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84945417336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824075     Document Type: Conference Paper

References (6)

1. H. Jong, L. Chen, T. Chiueh, "Parallel architecture for 3-Step Hierarchical Search block Matching Algorithm, " IEEE Trans, on Circuits and Systems for Video technology, vol. 4, No. 4, pp. 407-415, June, 1994.
2. C. H. Hsieh, T. P. Lin, "VLSI architecture for block-Matching Motion Estimation Algorithm, " IEEE Trans, on Circuits and Systems for Video technology, vol. 2, No. 2, pp. 169-175, June. 1992.
3. L. Vos, M. Stecherr, " Parameterizable VLSI Architectures for the Full-search Block-Matching Algorithm, " IEEE Trans, on Circuits and Systems, Vol. 36, No. 10, Oct. 1989.
4. N. Hayashi, T. Kitsuki, T. Shiraishi, T. Yokoyama, K. Oobuchi, Y. Ooi, S. Ikegami, N. Tokuda, H. Honma, I. Tamitani, T. Miyazaki, Y. Miyamoto, M. Ohta, " Compact Motion estimator with a Simplified Vector Search Strategy Maintaining Encoded Picture Quality, " IEEE Custom Integrated Circuits Conference, 1995.
5. H. Yeo, Y. Hen, "A Novel Modula systolic array architecture for Full-Search block Matching Motion Estimation, " IEEE trans! on circuit and systems for video technology, vol. 5, NO. 5, pp. 407-416, Oct., 1995.
6. K. Ishihara, S. Masuda, S. Hattori, H. Nishikawa, Y. Ajioka, T. Yamada, H. Amishiro, Yoshimoti, "A Half Precision MPEG-2 Motion-Estimation processor with Concurrent Three-Vector Search, " IEEE ISSCC, pp. 288-