NC-SRAM - A low-leakage memory circuit for ultra deep submicron designs

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 3-6

  Elakkumanan, P ^a   Narasimhan, A ^a   Sridhar, R ^a  

^a the State University of New York   (United States)

Author keywords

Capacitance; Circuits; Computer science; Design engineering; Energy consumption; Power dissipation; Power system reliability; Random access memory; Subthreshold current; Threshold voltage

Indexed keywords

CACHE MEMORY; CAPACITANCE; COMPUTER SCIENCE; DESIGN; ENERGY DISSIPATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT DESIGN; LEAKAGE CURRENTS; NETWORKS (CIRCUITS); RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

DESIGN ENGINEERING; LEAKAGE SAVINGS; MEMORY CIRCUITS; POWER SYSTEM RELIABILITY; RANDOM ACCESS MEMORY; SUB-THRESHOLD CURRENT; SUB-THRESHOLD LEAKAGE; ULTRA DEEP SUBMICRON DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 84945414668     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241450     Document Type: Conference Paper

References (13)

1. R.Stephany et. al., "A 200MHz 32b 0.5W CMOS RISC Microprocessor," ISSCC Digest of Technical Papers, Feb 1998, pp. 15.5-1-15.5-2.
2. H. Igura et. al., "An 800 MOPS 100mW 1.5V Parallel DSP for Mobile Multimedia Processing," ISSCC Digest of Technical Papers, Feb 1998, pp. 18.3-1-18.3-2.
3. T.Mori et al, "A Divided Word-line Structure in the Static RAM and it's applications to a 64K Full CMOS RAM", IEEE Journal of Solid State Circuits, vol. 18, pp. 479-484, Oct 1983.
4. Intel Corporation. Pentium III Processor for the SC242 at 450 MHz to1.13 GHz Datasheet, pp. 26-30.
5. M.Powell, K.Roy et al, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Cache Memories", Int. Symp. Low Power Electronics and Design (ISLPED), July 2000, pp 90-95.
6. C.H.Kim and Kaushik Roy, "Dynamic V, SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors", Int. Symp. Low Power Electronics and Design (ISLPED), Aug 2002, pp. 251-254.
7. L. Wei, Z. Chen, M. Johnson, K. Roy and V. De, "Design and optimization-n of low-voltage high-performance dual-threshold CMOS Circuits," in Proc. 35th Design Automation Conf., 1998, pp. 489-494.
8. K.Nii, H. Makino, Y. Tujihashi, C. Morishima, Y. Hayakawa, and Hahnmano, "A Low Power SRAM using Auto-Backgate-Controlled MTCMOS ", Proceedings of the Int. Symp. Low Power Electronics and Design, (ISLPED) 1998, pp. 260-271.
9. K. Flautner, N. S. Kim, S. Martin, D. Blaauw and Trevor Mudge, "Drowsy Caches: Simple Techniques for Reducing Leakage Power", International Symposium on Computer Architecture, June 2002, pp 148-157.
10. A. Agarwal, H. Li and K. Roy, " A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron," IEEE Journal of Solid State Circuits, vol. 38, pp. 319-328, Feb 2003.
11. S.Wolf, "Silicon Processing for the VLSI era Volume 3 - The submicron MOSFET," Lattice Press, 1995, pp. 213-222.
12. M.Yoshimoto, "A 64kb CMOS RAM with Divided Word Line Structure," 1983 IEEE International Solid State Circuits Conf., Digest of Technical Papers, pp. 58-59.
13. UC Berkeley Device Group. Berkeley Predictive technology Model. http://www-device.eecs.berkeley.edu/~ptm/.