FVP: A formal verification platform for SoC

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 21-24

  Liao, Wen Shiu ^a   Hsiung, Pao Ann ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

Clocks; Computer science; Emulation; Explosions; Formal verification; Hardware; Intellectual property; Process design; State space methods; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; COMPUTER HARDWARE; COMPUTER SCIENCE; EXPLOSIONS; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS; MODEL CHECKING; PROCESS DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; STATE SPACE METHODS; SYSTEM-ON-CHIP;

EMULATION; MODEL CHECKER; SOC DESIGNS; SYSTEM ON A CHIP; VERIFICATION PLATFORMS; VERIFICATION TECHNIQUES;

FORMAL VERIFICATION;

EID: 84945375816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241454     Document Type: Conference Paper

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