A new circuit model for power plane system considering decoupling capacitances in multi-layer digital applications

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2002-January, Issue , 2002, Pages 187-190

  Kim, Yong Ju ^a   Kang, Jong Ho ^a   Woo Park, Kun ^a   Wee, Jae Kyung ^a   Yoon, Han Sub ^a   Lee, Dong Ju ^a   Kim, Yong Tak ^a   Kee, Jung Sik ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; CIRCUIT THEORY; ELECTRONICS PACKAGING; FREQUENCY DOMAIN ANALYSIS; LUMPED PARAMETER NETWORKS; MATRIX ALGEBRA; TIME DOMAIN ANALYSIS;

DE-COUPLING CAPACITANCE; DECOUPLING CAPACITOR; DIGITAL APPLICATIONS; FREQUENCY DOMAINS; LUMPED CIRCUIT MODELS; MODELING TECHNIQUE; NODE ADMITTANCE MATRIX; POWER-GROUND PLANES;

INVERSE PROBLEMS;

EID: 84945268301     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2002.1057912     Document Type: Conference Paper

References (4)

1. J. Kim and M. Swaminathan, 'Modeling of Irregular Shaped Power Distribution Planes Using Transmission Matrix Method," IEEE, Trans., AP, Vol. 24, No. 3, pp. 334-346, Aug. 2001.
2. L. D. smith, "Decoupling capacitor calculations for CMOS circuits," in Ptoc. Elect. Elect. Packag. Conj, Nov. 1994
3. T. H. Hubing, et al,. "Power Bus Decoupling on Multilayer Printed Circuit Board," IEEE Trans., EMC. Vol. 37, No. 2, May 1995.
4. Keunmyung Lee and Alan Barber, "Modeling and Analysis of Multichip Module power Supply Planes," IEEE Trans. on components, packaging, and manufacturing-part B, Vol. 18, No. 4, Nov. 1995.