Effect of poly Si/ High-K interface on device reliability

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings

Volumn , Issue , 2003, Pages 324-325

  Wang, X W ^a   Bu, H M ^a   Ma, T P ^a   Tseng, H ^b   Tobin, Phil ^b  

^a YALE UNIVERSITY   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; GATE DIELECTRICS; HAFNIUM OXIDES; HOT CARRIERS; RELIABILITY; SEMICONDUCTOR DEVICES; SILICON NITRIDE; THRESHOLD VOLTAGE;

CONSTANT VOLTAGE STRESS; DEVICE PERFORMANCE; DEVICE RELIABILITY; HIGH- K GATE DIELECTRICS; HOT CARRIER INJECTION; HOT-CARRIER-INDUCED DEGRADATION; POLY-SI-GATE ELECTRODES; THRESHOLD VOLTAGE SHIFTS;

MOSFET DEVICES;

EID: 84945249662     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2003.1272116     Document Type: Conference Paper

References (1)

1. C. Hohbs, et al. "Fermi level pinning at the polySi/metal oxide interface", 2003 symposium on VLSI Technology Digest of Technical papers.