Methods for designing low-leakage power supply clamps

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2003-January, Issue , 2003, Pages

  Maloney, Timothy J ^a   Poon, Steven S ^a   Clark, Lawrence T ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SYSTEMS; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; LEAKAGE CURRENTS; LOGIC DESIGN; POWER SUPPLY CIRCUITS;

ESD PROTECTION CIRCUIT; LEAKAGE REDUCTION; LOW LEAKAGE POWER; LOW-POWER SEMICONDUCTOR COMPONENTS; MOS-FET; POWER CLAMPS; SINGLE GATES; SUPPLY VOLTAGES;

LOW POWER ELECTRONICS;

EID: 84945242654     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

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6. T.J. Maloney and T.M. Eiles, US Patent 5,907,464; issued May 25, 1999, assigned to Intel Corp.
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13. T.J. Maloney, US Patent 5,956,219, issued Sept. 21, 1999, assigned to Intel.
14. T.J. Maloney and W. Kan, "Stacked PMOS Clamps for High Voltage Power Supply Protection", 1999 EOS/ESD Symposium Proceedings, pp. 70-77.
15. Also published in Microelectronics Reliability 41, No. 3, pp. 335-348 (March, 2001).
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17. T.J. Maloney and W. Kan, "RC Timer Scheme", US Patent 6,510,033, issued Jan. 21, 2003, assigned to Intel.
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22. Revised version published in IEEE Trans. on Components, Packaging, and Manufacturing Technology-Part C, 19, 150-161, July 1996.
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