Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

Neurocomputing

Volumn 171, Issue , 2016, Pages 1606-1609

  Clemente, Juan Antonio ^a   Mansour, Wassim ^b   Ayoubi, Rafic ^c   Serrano, Felipe ^a   Mecha, Hortensia ^a   Ziade, Haissam ^d   El Falou, Wassim ^d   Velazco, Raoul ^b  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b TIMA LABORATORY   (France)

^c UNIVERSITY OF BALAMAND   (Lebanon)

^d LEBANESE UNIVERSITY   (Lebanon)

Author keywords

Artificial Neural Network (ANN); Fault tolerance; FPGA; Hopfield Neural Network (HNN); Single Event Transient (SET); Single Event Upset (SEU)

Indexed keywords

COMPUTER CONTROL SYSTEMS; DIGITAL STORAGE; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLASH MEMORY; HARDWARE; HIGH ELECTRON MOBILITY TRANSISTORS; HOPFIELD NEURAL NETWORKS; INTEGRATED CIRCUIT DESIGN; NEURAL NETWORKS; RADIATION HARDENING;

FAULT-TOLERANT; FPGA IMPLEMENTATIONS; HARDWARE IMPLEMENTATIONS; HOPFIELD NEURAL NETWORKS (HNN); SINGLE EVENT TRANSIENTS; SINGLE EVENT UPSETS; TRIPLE MODULAR REDUNDANCY;

TRANSIENTS;

ARTICLE; ARTIFICIAL NEURAL NETWORK; COMPUTER PROGRAM; CONTROLLED STUDY; DATA PROCESSING; FAULT TOLERANT HOPFIELD NEURAL NETWORK; FIELD PROGRAMMABLE GATE ARRAY; INTEGRATED CIRCUIT; PRIORITY JOURNAL; SINGLE EVENT TRANSIENTS; SINGLE EVENT UPSETS; TRIPLE MODULAR REDUNDANCY;

EID: 84944512347     PISSN: 09252312     EISSN: 18728286     Source Type: Journal    
DOI: 10.1016/j.neucom.2015.06.038     Document Type: Article

References (9)

1. D.E. Rumelhart, J.L. McClelland, C. PDP Research Group (Eds.), Parallel Distributed Processing: Explorations in the Microstructure of Cognition, Vol. 1: Foundations, MIT Press, Cambridge, MA, USA, 1986.
2. Normand E. Single event effects in avionics. IEEE Trans. Nucl. Sci. 1996, 43(2):461-474.
3. Hopfield J.J. Neurons with graded response have collective computational properties like those of two-state neurons. Neurocomputing: Foundations of Research 1988, MIT Press, Cambridge, MA, USA, pp. 577-583.
4. Stepanova M., Lin F., Lin V.C.-L. A Hopfield neural classifier and its FPGA implementation for identification of symmetrically structured DNA motifs. J. VLSI Signal Process. Syst. 2007, 48(3):239-254.
5. Mansour W., Ayoubi R., Ziade H., Velazco R., El Falou W. An optimal implementation on FPGA of a Hopfield neural network. Adv. Artif. Neural Syst. 2011, 2011. 7:1-7:9.
6. Wang Q., Shi W., Atkinson P., Li Z. Land cover change detection at subpixel resolution with a Hopfield neural network. IEEE J. Sel. Top. Appl. Earth Obs. Remote Sens. 2015, 8(3):1339-1352.
7. A. Kzar, M. MatJafri, H. Lim, K. Mutter, S. Syahreza, Modified Hopfield neural network algorithm (MHNNA) for TSS mapping in Penang strait, Malaysia, in: IEEE International Conference on Signal and Image Processing Applications (ICSIPA), 2013, pp. 187-192.
8. Mansour W., Velazco R. An automated SEU fault-injection method and tool for HDL-based designs. IEEE Trans. Nucl. Sci. 2013, 60(4):2728-2733.
9. V. Alaminos, F. Serrano, J.A. Clemente, H. Mecha, NESSY: an implementation of a low-cost fault-injection platform on a Virtex-5 FPGA, in: the Conference on Radiation and its Effects on Components and Systems (RADECS), 2012.