Double-latch clocking scheme for low-power I.P. Cores

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1918, Issue , 2000, Pages 217-224

  Arm, Claude ^a   Masgonty, Jean Marc ^a   Piguet, Christian ^a  

^a CSEM   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; FLIP FLOP CIRCUITS;

CLOCK GATING; CLOCK SKEW TOLERANCE; CLOCKING SCHEMES; D FLIP FLOPS; DEEP SUB-MICRON TECHNOLOGY; NONOVERLAPPING; REDUCED POWER CONSUMPTION; SINGLE PHASE;

CLOCKS;

EID: 84944203696     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45373-3_23     Document Type: Conference Paper

References (7)

1. M. Keating, P. Bricaud, “Reuse Methodology Manual”, Kluwer Academic Publishers, 1999.
2. C. Piguet et al. "Low-Power Design of 8-bit Embedded CoolRISC Microcontroller Cores", IEEE JSSC, Vol. 32, No 7, July 1997, pp. 1067-1078.
3. Ph. Mosch et al. “A 72W, 50 MOPS, 1V DSP for a hearing aid chip set” ISSCC’00, San Francisco, February 7-9, Session 14, paper 5.
4. J-M. Masgonty et al. "Low-Power Design of an Embedded Microprocessor", ESSCIRC'96, September 16-21, 1996, Neuchâtel, Switzerland
5. www.csem.ch, www.xemics.ch, www.coolrisc.ch
6. C. Piguet, “Low-Power Digital Design”, invited talk, CCCD Workshop at Lund University, March 9-10, 2000, Lund, Sweden.
7. J. G. Xi, D. Staepelaere, “Using Clock Skew as a Tool to Achieve Optimal Timing”, Integrated System Magazine, April 1999, webmaster@isdmag.com