Automatic verification on the large

Proceedings - 3rd IEEE International High-Assurance Systems Engineering Symposium, HASE 1998

Volumn 1998-November, Issue , 1998, Pages 134-141

  Wang, Farn ^a   Hsiung, Pao Ann ^a  

^a INSTITUTE OF INFORMATION SCIENCE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

GROUP THEORY; STATE SPACE METHODS; SYSTEMS ENGINEERING;

AUTOMATIC VERIFICATION; RESOURCE MANAGEMENT; STATE SPACE REPRESENTATION;

MANIPULATORS;

EID: 84944099474     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HASE.1998.731605     Document Type: Conference Paper

References (24)

1. R. Alur, R.K. Brayton, T.A. Henzinger, S. Qadeer, and S.K. Rajamani, "Partial-Order Reduction in Symbolic State-Space Exploration, " Intl. Conf. CAV97.
2. R. Alur, C. Courcoubetis, D.L. Dill. Model Checking for Real-Time Systems, IEEE LICS, 1990.
3. R. Alur, C. Courcoubetis, N. Halbwachs, D. Dill, and H. Wong-Toi, "Minimization of Timed Transition Systems, " Intl. Conf. CONCUR92, August 1992, Lecture Notes in Computer Science, Vol. 630, pp. 340-354.
4. R. Alur, T.A. Henzinger, P.-H. Ho. Automatic Symbolic Verification of Embedded Systems. in Proceedings of 1993 IEEE Real-Time System Symposium.
5. J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, L.J. Hwang. Symbolic Model Checking: 1020 States and Beyond, IEEE LICS, 1990.
6. A. Bouajjani, J-C. Fernandez, N. Halbwachs, and P. Raymond, "Minimal State Graph Generation, " Science of Computer Programming, Vol. 18, No. 3, 1992, pp. 247-269.
7. J. Bengtsson, B. Jonsson, J. Lilius, and W. Yi, "Partial Order Reductions for Timed Systems, " to appear in Procs. CONCUR 98.
8. R.E. Bryant. Graph-based Algorithms for Boolean Function Manipulation, IEEE Trans. Comput., C-35(8), 1986.
9. E. Clarke and E.A. Emerson. Design and Synthesis of Synchronization Skeletons using Branching-Time Temporal Logic, Proceedings ofWorkshop on Logic of Programs, Lecture Notes in Computer Science 131, Springer-Verlag, 1981.
10. E. Clarke, E.A. Emerson, and A.P. Sistla. Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications, ACM Transactions on Programming Languages and Systems 8(2), 1986, pp. 244-263.
11. C. Daws and S. Yovine, "Reducing the Number of Clock Variables of Timed Automata, " in Procs. Real-Time Systems Symposium, Dec. 1996, pp. 73-81.
12. E.A. Emerson, A.P. Sistla. Utilizing Symmetry whenModel-Checking under Fairness Assumptions: An Automata-Theoretic Approach. ACM TOPLAS, Vol. 19, Nr. 4, July 1997, pp. 617-638.
13. I.N. Herstein. Topics in Algebra, 2nd Edition, 1975, Xerox College Publishing, Lexington, Massachusetts.
14. K. Hoffman, R. Kunze. Linear Algebra, 2nd edition, 1971, Prentice Hall, Inc., Englewood Cliffs, New Jersey.
15. T.A. Henzinger, X. Nicollin, J. Sifakis, S. Yovine. Symbolic Model Checking for Real-Time Systems, IEEE LICS 1992.
16. K.G. Larsen, P. Pettersson, and W. Yi, "Compositional and SymbolicModel-Checking of Real-Time Systems, " in Procs. of the 16th IEEE Real-Time Systems Symposium, Dec. 1995.
17. K.G. Larsen and W. Yi, "Time Abstracted Bisimulation: Implicit Specifications and Decidability, " Intl. Conf. Mathematical Foundations of Programming Semantics, April 1993, Lecture Notes in Computer Science 802.
18. D. Peled, "All from One, One for All-on Model Checking Using Representatives, " Intl. Conf. CAV93, June 1993, Lecture Notes in Computer Science, Vol. 697, pp. 409-243.
19. S. Tripakis and S. Yovine, "Analysis of Timed Systems Based on Time-Abstracting Bisimulations, " Intl. Conf. CAV96, July 1996, Lecture Notes in Computer Science, Vol. 1102.
20. F. Wang, A.K. Mok, E.A. Emerson. Real-Time Distributed System Specification and Verification in APTL. ACM TOSEM, Vol. 2, No. 4, Octobor 1993, pp. 346-378.
21. F. Wang. Timing Behavior Analysis for Real-Time Systems. IEEE LICS 1995.
22. F. Wang. Reachability Analysis at Procedure Level through Timing Coincidence. in Proceedings of the 6th CONCUR, Philadelphia, USA, August 1995, LNCS 962, Springer-Verlag.
23. F. Wang, P.-A. Hsiung. Iterative Refinement and Condensation for State-Graph Construction. Technical Report TR-IIS-98-009, Institute of Information Science, Academia Sinica, Taipei, Taiwan, ROC.
24. F. Wang, C.T. Lo. Procedure-Level Verification of Real-Time Concurrent Systems.To appear in Proceedings of the 3rd FME, Oxford, Britain, March 1996; in LNCS, Springer-Verlag.