Reliability improvement of 9 nm-node Cu/low-k interconnects

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 262-264

  Matsumoto, S ^a   Ishii, A ^b   Tomita, K ^b   Hashimoto, K ^b   Nishioka, Y ^b   Sekiguchi, M ^a   Iwasaki, A ^c   Isono, S ^a   Satake, T ^a   Okazaki, G ^a   Fujisawa, M ^b   Matsumoto, M ^b   Yamamoto, S ^b   Matsuura, M ^b  

^a PANASONIC CORPORATION   (Japan)

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

^c Matsushita Semi Conductor Engineering Co Ltd   (Japan)

Author keywords

Atherosclerosis; Dielectrics; Failure analysis; Lithography; Reliability engineering; Semiconductor device reliability; Silicon carbide; Temperature; Testing; Ultra large scale integration

Indexed keywords

DIELECTRIC MATERIALS; ELECTROMIGRATION; FAILURE ANALYSIS; INTEGRATION TESTING; INTERDIFFUSION (SOLIDS); LITHOGRAPHY; NANOTECHNOLOGY; RELIABILITY; RELIABILITY ANALYSIS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SILICON CARBIDE; TEMPERATURE; TESTING; ULSI CIRCUITS;

ATHEROSCLEROSIS; BARRIER METAL DEPOSITION; BARRIER METAL THICKNESS; HIGH TEMPERATURE STORAGE TEST; INTERCONNECT RELIABILITY; RELIABILITY ENGINEERING; RELIABILITY IMPROVEMENT; SEMICONDUCTOR DEVICE RELIABILITY;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84944030186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219771     Document Type: Conference Paper

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