Optimizations for faster execution of Esterel programs

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 227-236

  Potop Butucaru, D ^a   De Simone, R ^b  

^a PSL RESEARCH UNIVERSITY   (France)

^b INRIA   (France)

Author keywords

Algorithm design and analysis; Analytical models; Clocks; Design optimization; Digital circuits; Embedded software; Embedded system; Hardware; Software algorithms; Software systems

Indexed keywords

ALGORITHMS; ANALYTICAL MODELS; CLOCKS; COMPUTER HARDWARE; COMPUTER SIMULATION LANGUAGES; DESIGN; DIGITAL CIRCUITS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ESTERS; FLOW PATTERNS; FORMAL METHODS; PROGRAM COMPILERS; SEMANTICS; STATIC ANALYSIS;

ALGORITHM DESIGN AND ANALYSIS; CODE GENERATION ALGORITHM; COMPILATION TECHNIQUES; DESIGN OPTIMIZATION; INTERMEDIATE MODEL; PROGRAM STRUCTURES; SOFTWARE ALGORITHMS; SOFTWARE SYSTEMS;

C (PROGRAMMING LANGUAGE);

EID: 84943638273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210107     Document Type: Conference Paper

References (10)

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3. G. Berry. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming, 19(2):87-152, 1992.
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7. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.
8. D. Potop-Butucaru. Fast redundancy elimination using high-level structural information from Esterel. RR 4330, INRIA, 2001.
9. D. Potop-Butucaru. Optimizations pour la simulation efficace de programmes Esterel. PhD thesis, Ecole des Mines, Paris, France, November 2002.
10. H. Toma. Analyse constructive et optimisation séquentielle des circuits générés à partir du langage synchrone réactif Esterel. PhD thesis, Ecole des Mines, Paris, France, September 1997.