The comparison and combination of CMOS inductor Q-enhancement techniques

IEEE High Frequency Postgraduate Student Colloquium

Volumn 2003-January, Issue , 2003, Pages 94-97

  Murphy, O ^a   Blackburn, J ^a   Murphy, P ^a   McCarthy, K ^a   Murphy, A ^b  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b MOTOROLA   (Ireland)

Author keywords

Circuit optimization; CMOS technology; Degradation; Energy consumption; Inductors; Microwave frequencies; Noise figure; Radio frequency; Silicon; Wireless LAN

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; ELECTRIC INDUCTORS; ENERGY UTILIZATION; MICROWAVE FREQUENCIES; SILICON; WIRELESS LOCAL AREA NETWORKS (WLAN);

CIRCUIT OPTIMIZATION; CIRCUIT PERFORMANCE; CMOS TECHNOLOGY; DIFFERENTIAL INDUCTORS; PATTERNED GROUND SHIELD; Q-ENHANCEMENT TECHNIQUES; RADIO FREQUENCIES; WLAN APPLICATIONS;

NOISE FIGURE;

EID: 84943549709     PISSN: 15466523     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HFPSC.2003.1242315     Document Type: Conference Paper

References (5)

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3. M. Soyuer, J. N Burghartz, K. A. Jenkins, S. Ponnapalli, J. F. Ewen, and W. E. Pence, "Multilevel monolithic inductos in silicon technology," Electronics Letters, vol. 31, no. 5, pp. 359-360, March 1995.
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