Accelerating bit error rate testing using a system level design tool

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 62-68

  Singh, V ^a   Root, A ^a   Hemphill, E ^a   Shirazi, N ^a   Hwang, J ^a  

^a XILINX INC   (United States)

Author keywords

Bit error rate; Circuit testing; Digital signal processing; Field programmable gate arrays; Hardware design languages; Life estimation; Mathematical model; Signal processing algorithms; System testing; System level design

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE; COMPUTERS; DESIGN; DIGITAL SIGNAL PROCESSING; ERRORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT DESIGN; LOGIC GATES; LOGIC SYNTHESIS; MATHEMATICAL MODELS; OPTICAL COMMUNICATION; SIGNAL PROCESSING; SIGNAL RECEIVERS;

CIRCUIT TESTING; HARDWARE DESIGN LANGUAGE; LIFE ESTIMATION; SIGNAL PROCESSING ALGORITHMS; SYSTEM LEVEL DESIGN; SYSTEM TESTING;

BIT ERROR RATE;

EID: 84942917851     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227242     Document Type: Conference Paper

References (16)

1. The Mathworks Inc., "Simulink, Dynamic System Simulation for Matlab, Using Simulink," Natick, Massachusetts, 1999.
2. J. Hwang, B. Milne, N. Shirazi, and J. Stroomer, "System Level Tools for DSP in FPGAs," FPL 2001, Lecture Notes in Computer Science, pp 534-543, 2001.
3. J. Hwang and J. Ballagh, "Building Custom FIR Filters Using System Generator," Field Programmable Logic and Applications, LNCS 2438, Springer, 2002, pp. 1101-1104.
4. Digital Video Transmission Standard for Cable Television. ANSI/SCTE 07 2000.
5. Digital Video Broadcasting (DVB);Framing structure, channel coding and modulation for digital terrestrial television ETSI EN 300 744 V1.4.1 (2001-01)
6. S. Lin and D. J. Costello, Error Control Coding : Fundamentals and Applications, Pearson Education, 1983.
7. Xilinx Data Sheet: Convolution Encoder V2.0, Xilinx, Inc. March 2002
8. Xilinx Data Sheet: Viterbi Decoder V2.0, Xilinx, Inc. March 2002
9. Xilinx Data Sheet: Reed-Solomon Encoder V3.0, Xilinx, Inc. March 2002
10. Xilinx Data Sheet: Reed-Solomon Decoder V3.0, Xilinx, Inc. March 2002
11. Xilinx Data Sheet: Interleaver/De-Interleaver V2.0, Xilinx, Inc. March 2002
12. A. Ghazel, E. Boutillon, J. L. Danger, G. Gulak and H. Laamari, "Design and Performance Analysis of a High Speed AWGN Communication Channel Emulator", IEEE PACRIM Conference, Victoria, B. C., Aug. 2001.
13. P. Chu and R. Jones, "Design Techniques of FPGA Based Random Number Generator", Military and Aerospace Applications of Programmable Devices and Technologies Conference, 1999.
14. P. Bellows, and B. Hutchings, "JHDL - An HDL for Reconfigurable Systems", in IEEE Symposium on FPGAs for Custom Computing Machines, K.L. Pocek and J. Arnold (eds.), IEEE Computer Society Press, 1998, pp. 175-184.
15. Alpha Data Systems, Simulink Board Support Blockset, http://www.alpha-data.com/simulink-bsb-dsheet.html.
16. Lyr Signal Processing, DSP Link, FPGA Link: DSP + FPGA co-design, hardware-in-the-loop co-simulation, http://www.signal-lsp.com/.